Inlaid Copper Multilevel Interconnections Using Planarization by Chemical-Mechanical Polishing
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or by reducing R. In this article we address the latter. R can be reduced by reducing the resistivity p and the length L of the interconnection metal, and by increasing the
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cross-sectional area of the interconnections. Increasing the interconnection area has little appeal since (1) the area occupied by interconnection lines is already an extremely large fraction of the chip area and (2) the fabrication requirements limit the thickness of the metal. Multilevel metallization (MLM) schemes using a low-resistivity metal like Cu have thus been proposed to reduce both p and L. Lowering L, in such schemes, is achieved by using vertical interconnections that span short horizontal distances on selected planar levels. Several key process developments affecting both the metal and interlayer dielectric are essential to fabricate the multilevel interconnections on a chip. Figure 1 shows an idealized device with MLM. Both the planarized metal and dielectric layers are an integral part of such an idealized scheme. Global planarization is required for two important reasons. First is the exacting lithography required on a large-area exposure with minimum depth of field, which may vary depending on the wavelength of the radiation used or available. An of ten-qupted planarization requirement is 1,500 A or better across a 3.5 cm X 3.5 cm exposure field or even across the entire wafer surface, if possible. The second reason relates to processing. A topography across the surface will require etching of vias of different depths at all levels. Planarized dielectrics/ metals will lead to identical vertical interconnection heights between all upper levels. Planarized surfaces will provide secondary
Drain Semiconductor
Metal 1 Metal 2 Metal 3
Dielectric 1 Dielectric 2 Dielectric 3
Figure 1. Idealized cross section of a multilayer metallization (MLM) scheme on a MOSFET.
MRS BULLETIN/JUNE 1993
Inlaid Copper Multilevel Interconnections Using Planarization by Chemical-Mechanical Polishing
advantages such as improvement in step coverage, which results in improved reliability of metal lines. Therefore, one must consider a multilevel scheme combining metal, dielectric, and planarization techniques. Currently, copper is being investigated as the interconnection metal. Copper, in spite of its low resistivity, has not found application in silicon ICs because of its (1) high diffusivity and deep levels in silicon, (2) poor adhesion to SiO2, and (3) reactivity with the environment.1 In addition, the dry etching of copper has been extremely difficult. All published accounts and our efforts at the New York State SEMATECH Center of Excellence have shown Cu etching feasible at temperatures of about 250°C where use of a suitable etch mask is difficult. One can envision a planarization technique in which inlaid metal interconnections (filling the vias and trenches precut in the dielectric) can be created using the so-called damascene approach.2 This technique has recently been employed to build 4-level WAI interconnection schemes.2"
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