Impact of Fabrication Process, Layout Variation and Packaging Process on Cu/Low-k Interconnect Reliability
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Impact of Fabrication Process, Layout Variation and Packaging Process on Cu/Low-k Interconnect Reliability Aditya Karmarkar1, Xiaopeng Xu2, Dipu Pramanik2, Xi-Wei Lin2, Greg Rollins2, and Xiao Lin2 1 TCAD DFM Solutions, Synopsys (India) Pvt. Ltd., My Home Tycoon, 4th Floor, Block A, Begumpet, Hyderabad, 500016, India 2 TCAD DFM Solutions, Synopsys, Inc., 700, East Middlefield Road, Mountain View, CA, 94043 ABSTRACT The industry trend towards smaller feature size and higher integration density leads to multi-level Cu/low-k interconnect schemes with reduced line width and spacing. Mechanical stress is generated during interconnect fabrication. The spatial distribution of the stress is strongly affected by the layout variation. The packaging process generates a global chip level stress that permeates to the local interconnect level. Stress related failures and yield loss are major areas of concern for Cu/low-k interconnects. The effects of fabrication process, layout variation, and packaging process on the final stress distributions in Cu/low-k interconnect structures are examined and the reliability impact of mechanical stress is assessed. INTRODUCTION Each new technology generation requires more metal layers in the interconnect structures because of the smaller feature sizes and greater integration density. To achieve lower RC delays, Cu metallization and low-k interlayer dielectrics are commonly used in advanced integrated circuits. Greater integration density also requires interconnects with smaller line width and spacing. Low-k dielectrics are typically characterized by low mechanical strength, low hardness and high porosity [1]. The thermal mismatch stresses induced by the fabrication process pose significant reliability challenges for the integration of Cu/Low-k interconnects because of the poorer mechanical characteristics of the low-k dielectrics [2]. The geometry and the pattern of the metal lines also have a significant impact on the thermomechanical stresses in multilevel interconnect structures, which in turn affect the interconnect reliability [3], [4]. Packaging process also introduces mechanical stresses in the metal lines and dielectric layers. Packaging induced mechanical stresses are responsible for interface de-lamination and subsequent yield loss [5]. This paper presents a numerical simulation based approach to assess the impact of the fabrication process; layout variation and packaging process on the mechanical stresses in Cu/Low-k interconnect structures. Correlations between the mechanical stress induced by various factors and the interconnect reliability are examined and strategies to mitigate stress related reliability failures and improve overall yield are proposed.
RESULTS AND DISCUSSION Process-induced stress Figure 1 (a) shows a three-dimensional (3D) structure consisting of five copper lines connected by copper vias. Fabrication process information and a mask file in GDSII format are directly utilized in our simulator [6]. The structure represents intermediate interconnect
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