Cobalt Silicidation on Sub 100nm Hole Patterned Vertical Diode Formed by Silicon Epitaxial Growth and Its Electrical Pro
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1079-N08-06
Cobalt Silicidation on Sub 100nm Hole Patterned Vertical Diode Formed by Silicon Epitaxial Growth and Its Electrical Properties Min Yong Lee, K. B. Lee, H. S. Lee, S. J. Chae, I. K. Han, H. S. Kang, and S. W. Park R&D, Hynix Semiconductor Inc., San 136-1 Ami-ri Bubal-eub Icheon-si, Icheon, 467-701, Korea, Republic of ABSTRACT Self-aligned Cobalt silicide as ohmic contact layer on sub 100 nm hole patterned Si vertical diode formed by silicon epitaxial growth (SEG) is investigated and silicon epitaxial growth of higher than 4000 Å thickness and good crystalinity for PN diode has been successfully developed. Also, electrical isolation of 100 nm pitch size between diode and diode, and removal of unreacted Co/Ti/TiN layer have been realized by dip-out process without CMP simultaneously. Through the mechanism of void formation due to the variation of Si consumption rate during silicidation at limited hole pattern dimension, critical Co and Capping Ti thickness are investigated as various hole dimensions (80~120 nm), and then with p+ type dopant species (49BF2, 11B). The ratio of Co thickness to hole dimension demonstrates void free cobalt silicidation on various pattern sizes of silicon epitaxial growth. Silicon epitaxial growing PN diodes including void free CoSi2 show excellent electrical performance, especially lower than 10 pA reverse off leakage current.
INTRODUCTION Ohmic contact layer forming by Co salicide process is useful for low resistive and high performance device characteristics in very large scale integration (VLSI) circuit. The use of Co silicide has been limited by the degradations of junction leakage and operation current [1-3]. The degradation is caused by a pattern dependent silicidation rate and void formation. The Co silicidation process is very sensitive to the cobalt layer thickness, Ti capping layer quality, P-type dopants and hole dimension [3-6]. Therefore exact understanding about silicidation mechanism is necessary for getting good diode properties. In this work, we investigate the influence of Co/capping Ti Thickness, dopant species and hole dimension on silicidation rate and void generation at silicon epitaxial growing (SEG) diode hole contact.
EXPERIMENT We investigated the variation of Co silicidation as a function of thickness of cobalt with capping Ti/TiN which was deposited by PVD. Silicon epitaxial growth (SEG) was prepared as a substrate on the a patterned hole structure with a diameter of 100nm. After interlayer dielectric(ILD) oxide layer 100 nm hole patterning, Vertical diode was formed by silicon epitaxial growth(SEG) higher than 4000 Å, and then CMP was performed for isolation between diode to diode. To compare the dopant effect, BF2+ and B+ were implanted for P-type formation of vertical diode, respectively. And then RTA was preformed for dopant activation and
implantation induced damage reduction. Co/Ti/TiN layers were deposited subsequently in a conventional sputter just after HF wet cleaning. 1st low temperature RTA(500 °C, 60 s) was processed to form silicid
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