Demonstration of the state-of-the-art of formation and characterization of ultra-shallow junctions
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Demonstration of the state-of-the-art of formation and characterization of ultra-shallow junctions P. Borden, A. Al-Bayati1, J. Madsen, C. Lazik1, P. Carey1, L. Bechtler, and A. Mayur1 Boxer Cross Inc., 978 Hamilton Court Menlo Park, CA 94025, USA 1 Applied Materials, 3050 Bowers Ave. Santa Clara, CA 95054, USA ABSTRACT Doping process windows are becoming very narrow as VLSI technology nodes scale to smaller and smaller dimensions. The time and cost required to develop new doping methods and the desire to re-use equipment will make it likely that current methods will be applied as long as possible. This means that existing process tools will have very tight stability and uniformity requirements, and metrology will be required to drive process control. The paper describes the state-of-the-art of both doping processes involving ion implantation and spike annealing, and new metrology based on Carrier Illumination™ methods that will be required to implement inline process control for these processes. CI offers depth resolution on the order of 1Å, providing a level of control required to extend existing doping methods. The prospects of new methods such as Laser Thermal Annealing (LTA) are also discussed. INTRODUCTION VLSI scaling is approaching the limits of existing doping processes. While these processes – low energy implantation into amorphized layers with spike annealing [1] – can meet the requirements of the 100 nm node, the process window is very narrow. There is a strong motivation to continue existing processes as long as possible. Factors include equipment reuse and the cost, time and risk associated with developing alternate methods. This is analogous to lithography, where the same considerations have motivated extension of conventional exposure methods far beyond what was once thought possible. The desire to extend processes into narrower and narrower windows makes control of small variations in these complex, multi-step processes critical. This control will come in two ways: improved implanter and annealer performance, and improved metrology. The former will require very tight control of energy, dose, anneal temperature, temperature ramp profile, and uniformity of all processes. The latter will require in-line metrology on product wafers. Measurements on test wafers will not be sufficient, both because of the cost of large diameter substrates and because of the inter-relation between the series of process steps that cannot be captured by monitoring a single step. Of particular importance is the effect of process variation on device performance, so that measurements and process control tolerances reflect limits based on allowable electrical tolerance. These limits can be determined empirically or through device modeling. Figure 1, for example, shows an example of the relation between drive current and junction depth [2] for 180 nm NMOS transistors, with the junction depth measured on patterned wafers after the extension J2.4.1
anneal using Carrier Illumination™ (CI) methods [3,4]. These results show that a 2
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