Design and analysis of dual-gate misalignment on the performance of dopingless tunnel field effect transistor
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Design and analysis of dual‑gate misalignment on the performance of dopingless tunnel field effect transistor Deep Shekhar1 · Ashish Raman1 Received: 27 January 2020 / Accepted: 8 May 2020 © Springer-Verlag GmbH Germany, part of Springer Nature 2020
Abstract The submitted work presents a designed and analyzed dopingless double-gate tunnel field effect transistor. In the designed dopingless structure, doping is introduced by charge plasma technique and silicon is used as a choice of material. Initially, gate misalignment was done by shifting the bottom gate away from the drain region and toward the drain region by 50% and 100% amount. Further, both gates (top and bottom) have been misaligned by 50% and 100% for analyzing the device for analog and linearity performance. Analog parameters, device parameters and linearity parameters were calculated in order to understand the device behavior. By misaligning gates, it is found that when the bottom gate is shifting away from the source region, both gates have been misaligned by 100% showing that analog and linearity performance of the devices degrades. When the bottom gate is shifted toward the source, both gates have been misaligned by 50% providing better analog and linearity performance. Among all the misaligned structures, when both gates have been misaligned by 50% gives the best result such as ON-state current, OFF-state current, ION/IOFF, and subthreshold slope are 2.3 µA, 5.07 aA, 4.5 × 1 011 and 32 mV/decade respectively. Keywords Tunneling · Dopingless · Misalignment · Tunnel field effect transistor · Subthreshold slope · ON current
1 Introduction As the miniaturization of circuits has taken place by scaling down the metal oxide semiconductor field effect transistors (MOSFETs) [1], scaling down the MOSFET [2] or Fin-FET [3] introduces a number of short-channel effects (SCEs) and higher leakage current (OFF-state current) which degrade the device performance [4]. Further, scaling is affected by the stringent power constraints and subthreshold slope that is non-scalable [4]. The theoretical limit of the subthreshold slope for a MOSFET is 60 mV/decade [5]. To reduce the subthreshold swing for MOSFET below 60 mV/decade is very difficult. Therefore, intensive research is going on to find the alternative devices that could replace MOSFETs to achieve * Deep Shekhar [email protected] Ashish Raman [email protected] 1
VLSI Lab, Department of Electronics and Communications, Dr. B. R. Ambedkar, National Institute of Technology, Jalandhar 144011, India
lower power dissipation and lower subthreshold swing as compared to MOSFET. One of the most efficient devices is tunnel field effect transistor (TFET) [6, 7] because of its lower OFF-state current, higher ION/IOFF, lower subthreshold swing, threshold voltage and capability in suppressing the various SCEs [8–11]. For low voltage applications, Field effect transistor (FET)-based devices may not be used because of their higher subthreshold slope and low ON-current-to-OFFcurrent ratio (ION/IOFF). TFET provides an alt
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