Performance Analysis of Group IV Material Based Tunnel Field Effect Transistor: Effect of Drain Splitting and Introducin
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ORIGINAL PAPER
Performance Analysis of Group IV Material Based Tunnel Field Effect Transistor: Effect of Drain Splitting and Introducing Ge-Strip at Source- Channel Junction Surender Kumar 1
&
Rajesh Mehra 1 & Harsh Yadav 2 & Rikmantra Basu 2
Received: 26 September 2020 / Accepted: 3 November 2020 # Springer Nature B.V. 2020
Abstract The performance effect of splitting and abrupt doping in the drain region, use of a Ge strip at source-channel junction in group IV material based (Ge1 − xSnx/ Si1 − y − zGeySnz) Tunnel Field Effect Transistor (TFET) is investigated in the present manuscript. The variation of certain device parameters, such as mole fraction, different gate dielectrics, gate dielectric thickness and drain doping concentrations are applied to analyze the performance of proposed group IV material based TFET in terms of current-voltage (IV) characteristics, potential profile and ION/IOFF ratio using device simulator SILVACO TCAD. The simulation results obtained for the proposed TFET structure are compared with the other TFET structures available in the literature, which shows better results as ION/IOFF ratio was received of the order of 1012 in comparison to conventional group IV material based TFET and subthreshold swing of 25.03 mV/decade, which makes the proposed structure promising for high speed switching action with low power CMOS compatibility. Keywords Subthreshold Swing (SS) . Ambipolar behavior . Tunnel field effect transistor (TFET) . ON current to OFF current (ION/ IOFF) ratio . TunnelingGe1 − xSnx/ Si1 − y − zGeySnz, etc.
1 Introduction With the advancement and improvement in the technology, the market for portable products like smartphone, smartwatch, tablet, and notebook was growing due to which the demand for high scalability of CMOS (Complementary Metal Oxide Semiconductor) devices are increased. With the downscaling
* Surender Kumar [email protected] Rajesh Mehra [email protected] Harsh Yadav [email protected] Rikmantra Basu [email protected] 1
Department of Electronics and Communication Engineering, National Institute of Technical Teachers’ Training and Research, Chandigarh, India
2
Department of Electronics and Communication Engineering, National Institute of Technology Delhi, Delhi, India
of the transistor, threshold voltage (Vth) and supply voltage (Vdd) must be reduced, by doing so, the overdrive (Vdd − Vth) factor remains high to meet the performance requirements [1]. As Vth reduces, the off-state current (IOFF) increases exponentially. However, to reduce IOFF, sub-threshold swing (SS) must be reduced. In case of MOSFET, at room temperature, there was a physical restriction on the SS of 60 mV/decade because of the constant value of the KbT/q thermal voltage, (where Kb is the Boltzmann constant, T is the absolute temperature and q is the charge of an electron) [2, 3]. The large value of SS caused a leakage current of the high value in the subthreshold part with the reduction in the device size. Furthermore, as per Moore’s law, in the integrated c
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