Design and Performance Evaluation of Sub-10 nm Gaussian Doped Junctionless SOI and SELBOX FinFET
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ORIGINAL PAPER
Design and Performance Evaluation of Sub-10 nm Gaussian Doped Junctionless SOI and SELBOX FinFET Satya Prakash Singh 1,2
&
Md. Waseem Akram 1
Received: 4 March 2020 / Accepted: 10 August 2020 # Springer Nature B.V. 2020
Abstract In this paper influences of uniform and non-uniform doping on the performance of SOI and SELBOX FinFET at gate length of sub-7 nm are evaluated. Junctionless devices require very heavy and uniformly doped very thin channel. It adversely affects the performance such as reduction in on-current, increased off-current, and degradation in short channel behavior. Due to technical limitations, the doping profile becomes non-uniform in the vertical direction. In this simulation studies we use Gaussian doping profile in the vertical dimension to get non-uniform doping profile. The simulations are performed using Silvaco TCAD. Firstly, the performance of uniformly doped SOI and SELBOX Transistors are analyzed and compared. Furthermore, non-uniformly doped SOI and SELBOX FinFETs are analyzed and compared. Comparison is done on the basis of parameters ION, IOFF, ION/ IOFF ratio, DIBL, VTH, and SS etc. The simulation results show that the multi-gate structure with SELBOX technology gives best results under non-uniform doping profile. Keywords Junctionless transistor (JLT) . Silicon on insulator (SOI) FinFET . Selective buried oxide (SELBOX) FinFET
1 Introduction As the scaling of the devices goes down, it becomes severely difficult to produce very large concentration gradient at source-channel and channel-drain junctions. Junctionless transistors (contains no junction along the conduction path) were introduced in 2009 and have been extensively studied since onwards [1–7]. This device has very heavy and uniform doping in all the three regions of the device. In these devices, carriers are depleted from the channel in the off-state and bulk conduction takes place in the on-state. Fabrication process of these JLTs has become very simple and no need of large concentration gradient. Bulk conduction avoids surface scattering [8–11]. However, JLTs also face many problems. It requires ultrathin heavily and uniformly doped device layer.
* Md. Waseem Akram [email protected] Satya Prakash Singh [email protected] 1
Department of Electronics and Communication Engineering, Jamia Millia Islamia University, New Delhi, India
2
KIET Group of Institutions, Delhi-NCR, Ghaziabad, India
It is technically very difficult to achieve in the vertical direction. Secondly, in case of uniform doping, charge carriers deplete more from top of the channel than the bottom due to lesser control of gate on the lower part of the channel. So, leakage current increases. SOI FinFET has many advantages such as high drive current, low parasitic capacitance and better suppression of short channel behavior. The subthreshold leakage current has reasonable magnitude and it runs in the lower part of the channel in SOI FinFET. This is due to the fact that lower part of the channel does not get effectively depleted from cha
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