Design and FPGA Synthesis of an Efficient Synchronous Counter with Clock-Gating Techniques
In the proposed work, we focused on clock-gating-based synchronous counter. This paper depicts the designing of high-speed synchronous counter with low dynamic power dissipation using clock-gating method. We study the various design technique to overcome
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Abstract In the proposed work, we focused on clock-gating-based synchronous counter. This paper depicts the designing of high-speed synchronous counter with low dynamic power dissipation using clock-gating method. We study the various design technique to overcome the dynamic power dissipation in the synchronous circuit. After analysing the several techniques, we focused on clock-gating technique to minimize the dynamic power dissipation and compare the proposed counter to the previous counter in terms of latency, on-chip power dissipation, utilized area, and maximum operating frequency. The clock-gating technique enables for an improvement of 24, 36, and 31%, respectively, for latency, area, and maximum operating frequency as well as maintaining the on-chip power dissipation as the prior synchronous counter. The design proposal of 4-, 8-, and 16-bit synchronous counter is built by Verilog HDL code and synthesis is carried out with Spartan 3 FPGA on ISE design suit 14.2 Tool. Keywords Synchronous counter · Clock gating · Latency · On-chip power dissipation · Verilog HDL · Spartan-3 FPGA
1 Introduction A counter is a special type of register that goes through a pre-determinant sequence of state. As the name offer, counter enforces counting such as time and electronics pulses. Counters are extensively used in processor, calculator, real-time clock, etc.; S. K. Singh (B) · M. D. Gupta · R. K. Chauhan Department of Electronics and Communication Engineering, Madan Mohan Malaviya University of Technology, Gorakhpur, India e-mail: [email protected] M. D. Gupta e-mail: [email protected] R. K. Chauhan e-mail: [email protected] © The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2021 V. Nath and J. K. Mandal (eds.), Nanoelectronics, Circuits and Communication Systems, Lecture Notes in Electrical Engineering 692, https://doi.org/10.1007/978-981-15-7486-3_27
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in modern technology, high-speed counters are simulated which is used in machine moving control, digital clock, etc. Initially, counters are two types, synchronous and asynchronous; clock is the fundamental distinction between both of them. In asynchronous counter, the flip-flop is triggered either by the clock pulse or by the output of neighboring flip-flop, but in case of synchronous counter, all the flip-flop are triggered by an ordinary clock pulse. In modern automation technology, some event is very fast which cannot be detected in the program cycle. To detect such high-speed event, introducing a new technique term as high-speed counter (HSC). HSC is advantageous when determining the speed of rotary motion in case of only one or few pulses per rotation, and a part of this HSC is applicable at automation and process control, programmable logic controller, motor and stepper drives, and motion control application. In designing of minimum dynamic power and highly reliable synchronous counter, there are two crucial factors occurring: first one, in synchronous counte
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