Development of A 4H-SiC CMOS Inverter
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0911-B13-02
Development of A 4H-SiC CMOS Inverter Brett A. Hull1, Sei-Hyung Ryu1, Husna Fatima1, Jim Richmond1, John W. Palmour1, and James Scofield2 1 Cree, Inc., Durham, NC, 27703 2 Air Force Research Laboratory, Wright-Patterson AFB, OH, 45433
ABSTRACT In this paper we report the first 4H-SiC CMOS inverter, which was designed to be integrated in the process flow of a 4H-SiC power DMOSFET. The channels of both of the n-channel and p-channel MOSFETs of the inverter were 50 µm wide by 3 µm long. NMOSFET threshold voltage (VTH) ranged from 4.4 V at 25°C to 2.2 V at 250°C and PMOSFET VTH ranged from -4.75 V at 25°C to just under -4 V at 300°C. The transfer threshold voltage (Vm) of the 4HSiC CMOS inverter was in a very tight range of 2.8 V to 2.9 V over the entire temperature range of 25°C to 300°C when using a drive voltage (VDD) of 10 V. INTRODUCTION The advances in the technology of 4H-SiC Power MOSFETs and PiN diodes have been rapid over the past few years. 4H-SiC DMOSFETs designed to block up to 1200 V and conduct up to 5 A with a switching cycle on the order of 100 ns [1] and PiN diodes designed to block up to 6 kV and conduct up to 50 Amps with a reverse recovery time of 250 ns [2] have been reported. These devices have the capability of running at junction temperatures in excess of 300°C, reducing the complexity of the required active cooling systems involved in power handling applications. However, system drive circuits that are based on Si electronics must be well isolated from these SiC power devices due to the temperature limitations of Si-based logic circuits. In order to maximize the benefits of 4H-SiC power devices in power handling systems, the control circuitry will optimally be integrated directly with a 4H-SiC power device in a system-on-a-chip approach. Thus, an investigation of the feasibility of 4H-SiC logic devices is warranted. The complementary MOS inverter is an ideal test device on which to examine the feasibility of 4H-SiC CMOS logic devices and to investigate 4H-SiC CMOS suitability at operating temperatures of up to 300°C. Digital logic circuits fabricated in 6H-SiC have been examined previously [3,4], but we are for the first time demonstrating a CMOS inverter in 4HSiC. DEVICE PROCESSING A simplified cross-section of the 4H-SiC CMOS inverter is shown in Fig. 1. A 10 µm thick N-doped (6 x 1015 cm-3) n- epitaxial layer was grown on a 3 inch 4H-SiC wafer cut 4° off of the [0001] axis. The p-well and p+ regions were formed with Al implants, and a N implant was used to form the n+ regions. The source/drain implants were implanted in multi-energy
Figure 1. Schematic cross-section of the 4H-SiC CMOS Inverter. doses to give box-like profiles. The n+ source/drain regions of the n-channel MOSFET were doped at 1 x 1020 cm-3 and extended approximately 300 nm deep. The p+ source/drain regions of the p-channel MOSFET were doped at 2 x 1019 cm-3 and extended about 500 nm deep. The pwell implant was optimized for 4H-SiC DMOSFET fabrication [1], the peak doping of which was 4 x 1019 cm-3, extending a
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