Direct Observations of Relaxation of Strained Si/SiGe/Si on Insulator
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1262-V05-01
Direct Observations of Relaxation of Strained Si/SiGe/Si on Insulator
Tongda Ma and Hailing Tu General Research Institute for Nonferrous Metals, No.2 Xinjiekouwai Street, Beijing, 100088, P. R. China
ABSTRACT Microstructural evolution is directly observed when the cross-sectional film specimen of Si/SiGe/Si on insulator (Si/SiGe/SOI) is heated from room temperature (R.T., 291 K) up to 1113 K in high voltage transmission electron microscope (HVEM). The misfit dislocation at the lower interface of the SiGe layer begins to extend downwards even at 913 K. The lower interface takes the lead in roughening against the upper interface of the SiGe layer. The roughened interface is ascribed to elastic relaxation. As misfit strain is partially transferred to SOI top Si layer and misfit dislocation is prolonged at the lower interface, the roughened interface turns smooth again. Thereafter, the misfit dislocations are introduced into the upper roughened interface of the SiGe layer to release the increased misfit strain. It is suggested that the microscopic relaxation of the SiGe layer is related to dislocation behavior and strain transfer. INTRODUCTION The past several years have witnessed rapid growth in the study of strained Si on insulator due to its potential ability to improve the performance of very large scale integrated circuits [1]. In order to fabricate tensile strained Si capping layer, some creative methods have been reported on the basis of different mechanisms [2-5]. Most of mechanisms essentially depend on the compliancy of buried oxide (BOX) under high temperature. To evaluate the strain engineering, transmission electron microscopy (TEM) and high resolution x-ray diffractometry (HRXRD) are usually adopted to characterize the strain transfer and defect behavior [4, 5]. As a useful complementarity, in-situ TEM is performed to trace strain relaxation of the SiGe or Si/SiGe on bulk Si [6-8]. However, few in-situ TEM works have ever been focused on Si/SiGe/SOI by now. It is demonstrated that strained Si/SiGe/SOI can be achieved by the successive deposition of the Si buffer, the SiGe layer and the Si capping layer on a bonded SOI wafer and the following in-situ thermal treatment [9]. TEM, triple-axis x-ray diffractometer (TAD), and secondary ion mass spectrometer (SIMS) have been employed to investigate defects, strain, and interdiffusion within Si/SiGe/Si on insulator. In this work, HVEM is used to observe microstructral evolution of Si/SiGe/SOI during in-situ annealing in order to further clarify the mechanism of strain relaxation. EXPERIMENTAL DETAILS
Si/SiGe/SOI is grown in the ultra-high vacuum chemical vapor deposition (UHV/CVD) system. The starting bonded SOI substrate is chemically cleaned for 15 minutes in a boiled solution of H2SO4:H2O2 (4:1), then rinsed in de-ionized water for at least 10 minutes. Native oxide on the wafer surface is etched in 10% HF solution for 30 seconds and then ferried into the loading chamber. When the vacuum reaches 10-5 Pa, the wafer is put into the growth chamber.
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