Strain relaxation of strained-Si layers on SiGe-on-insulator (SGOI) structures after mesa isolation
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Strain relaxation of strained-Si layers on SiGe-on-insulator (SGOI) structures after mesa isolation Koji Usuda, Tomohisa Mizuno, Tsutomu Tezuka, Naoharu Sugiyama, Yoshihiko Moriyama, Shu Nakaharai and Shin-ichi Takagi MIRAI Project, ASET, 1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki 212-8582, Japan. ABSTRACT Strained-Si-On-Insulator (Strained-SOI) MOSFETs are one of the most promising device structures for high speed and/or low power CMOS. In realizing strained-Si MOS LSI, fabrication of strained-Si MOSFETs with small sizes are indispensable and thus, the investigation of the strain relaxation is an important issue. Therefore, the strain relaxation of strained-SOI mesa islands with small active area was investigated in this study. Thin strained-Si films were grown on thin relaxed SiGe-on-insulator (SGOI) structures (x=0.28). The isolation process was carried out by using chemical-dry-etching (CDE) to fabricate samples with small active areas. Using Raman spectroscopy with resolution of > 1 micron meter, strained-Si islands on SGOI substrates with the size of 5 micron meter square were investigated. Rapid-thermal-annealing (RTA) in N2 atmosphere was performed to study the strain relaxation during heating processes. As a result, it was confirmed that the strained-Si layers grown on relaxed SiGe (x=0.28) before and after mesa isolation, down to 5 micron meter in size, had almost no relaxation after the RTA process at 1000°C. Furthermore, it was confirmed that the nano-beam electron diffraction (NBD) measurement showed similar tendency regarding the strain relaxation.
INTRODUCTION A strained-Si MOSFET device [1] is attractive because of the electron and hole mobility enhancement [2,3] and the compatibility with standard Si ULSI processes. Furthermore, a combination of strained-Si channel on thin SiGe and SOI structure can be the optimum structure to realize high speed and/or low power MOSFETs. In this device structure, a strained-Si layer is fabricated on relaxed SiGe-On-Insulator (SGOI) virtual substrates. Due to the mismatch of lattice constant between SiGe and Si, tensile strain is induced in the Si channel layer. As a result, the MOSFET fabricated with the strained-Si channel layer exhibits higher electron and hole mobility than that of the bulk-Si channel, and also shows lower parasitic capacitances of source and drain region due to SOI structure. On the other hand, when designing strained-Si MOS LSI, fabrication of strained-Si MOSFETs with small active areas of micron meter size or less is necessary. However, the strain relaxation in a strained-SOI layer, the influence of fabrication process limitation and the relaxation mechanism have not been studied in detail yet. Particularly, it is important to confirm whether the strain in the strained-SOI structures can be maintained after the device isolation. In this paper, we examine two topics about the strain relaxation of strained-Si layers on SGOI structures, by using Raman measurements and nano-beam electron diffraction (NBD) method [4]. First, we evaluate t
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