Fabrication of Strained Silicon on Insulator (SSOI) by Direct Wafer Bonding Using Thin Relaxed SiGe Film as Virtual Subs
- PDF / 647,747 Bytes
- 6 Pages / 612 x 792 pts (letter) Page_size
- 88 Downloads / 249 Views
B2.2.1
Fabrication of Strained Silicon on Insulator (SSOI) by Direct Wafer Bonding Using Thin Relaxed SiGe Film as Virtual Substrate J.J. Lee, J.S. Maa, D. J. Tweet, and S.T. Hsu Sharp Labs of America, 5700 NW Pacific Rim Blvd Camas, WA 98607, USA ABSTRACT NMOS devices have been successfully fabricated on SSOI wafers. The SSOI wafer fabrication is by direct wafer bonding and wafer transfer by splitting of the strained Si on thin SiGe virtual substrate to an oxidized wafer. The thin SiGe virtual substrate is fabricated by strained SiGe deposition, H2+ implantation, and SiGe lattice relaxation anneal. This relaxation process creates a confined defect zone at the SiGe to Si substrate interface that ensures low defect strained Si growth. 10 µm by 10 µm NMOS SSOI devices show an improvement of 100% in drive current and 115% in transconductance. A near ideal subthreshold swing was observed on NMOS devices with channel length as short as 0.1 µm. INTRODUCTION Carrier transport enhancement by the use of a strained-Si channel leads to a CMOS technology with improved speed or reduced power on the same technology node. Biaxial tensile strain in a Si film on a relaxed SiGe lattice splits the 6-fold degeneracy in the conduction band of Si as well as the degeneracy between the light hole and heavy hole in the valence band of Si. This reduces the inter-valley and inter-band scattering for electrons and holes in the conduction band and valence band, respectively, and reduces the effective transport mass for both electrons and holes. As a result, higher electron and hole mobility devices can be fabricated on strained Si wafers. To further improve the performance of strained Si devices, strained Si on insulator (SSOI) technology has been proposed [1-4]. SSOI CMOS devices combine the benefits of strained Si devices and SOI devices. The SSOI wafer fabrication in this paper is based on the fabrication of strained Si on thin SiGe virtual-substrates [5-7] and the fabrication of SmartCutTM SOI wafers [8]. Graded SiGe was grown on Si wafers without relaxation with the SiGe thickness in the range of 0.25 µm to 0.35 µm. Hydrogen was implanted into the SiGe and Si interface. During the subsequent heat treatment, the implanted H2 forms a narrow defect band at the interface and enhances the nucleation of misfit dislocations. This results in enhanced strain relaxation in the SiGe epilayer, while keeping most of the threading dislocations away from the SiGe surface. After CMP to remove the surface roughness, strained Si was epitaxially deposited on the thin relaxed SiGe layer. Next, hydrogen ions were implanted into the Si substrate to create a splitting plane. The strained Si on thin SiGe virtual-substrate was then bonded to a handle wafer which was covered with thermal oxide. After splitting, SiGe was selectively removed, resulting in a strained Si film directly on buried oxide (BOX). Details of the SSOI wafer process steps will be reported. Normarski optical microscopy was used to qualitatively determine surface roughness. Relaxation in the SiG
Data Loading...
