Directional Sputter Deposition for Semiconductor Applications
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1. INTRODUCTION The design and manufacturing of integrated circuits has gone through 2 generations and is embarking on a third. The first generation consisted of photoresistbased lift-off processing, in which metal films were evaporated through photoresist surface masks which were subsequently removed ("lifted off") by a solvent. This was followed by a Reactive-Ion-Etching (RIE) generation, in which mostly planar films were patterned by RIE through surface masks. Both of these generations resulted in low aspect ratio (AR) features which were fairly wide and not very thick. The coming, third generation is known as "damascene" processing. In this process sequence, planar dielectric films are patterned with embedded lines (trenches) and holes (vias). A subsequent deposition step fills the embedded feature with a metal or compound, and the final step is a Chemical-Mechanical Polish (CMP) in which the wafer is polished flat, down to the original dielectric surface, removing any over-deposited film on top of the dielectric. The result is then an embedded line or via with a top surface flush with that of the planar dielectric film. This entire process can be repeated several times to build up the multiple layer interconnection circuits necessary for high density integrated circuits. The intrinsic advantage with damascene processing is that it is self-planarizing. Ideally any number of layers (lines/vias in dielectric) can be added to form increasingly complicated, three dimensional circuits. In addition, due to the ability to etch fairly high AR features, the circuits can be packed more tightly together, reducing RC-time constant limits on circuit performance. The fundamental disadvantage with damascene processing is that the deposition of metal films into high AR features can be difficult, particularly if the materials choice and electrical performance are critical. For example, high AR features can often routinely be 503
Mat. Res. Soc. Symp. Proc. Vol. 354 01995 Materials Research Society
filled with CVD processes, which are highly developed for W. This is appropriate for via (stud) connections, but too resistive for long line interconnects. While there has been significant effort in the past several years, extending CVD technology to AICu or Cu has proven to be a complicated and sophisticated problem, particularly for AICu. These materials are required primarily for their high electrical conductivity, compared to W. CuCVD has been intensely studied recently [1], but the transition to this technology requires significant changes in the various technologies and materials used in processing. 2. PHYSICAL VAPOR DEPOSITION Sputter deposition has been routinely used for the blanket metal depositions needed for the RIE-based process technology, primarily for AICu. However, as the AR of features increases above about 0.75, physical sputtering tends to result in void formation during the filling of a feature due to the mostly isotropic nature of the sputtering process and the system geometry. Without some modification, conven
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