Effect of N + Ion Implantation and Gox Process on in and B Channel Profile
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EFFECT OF N+ ION IMPLANTATION AND GOX PROCESS ON In AND B CHANNEL PROFILE G.Curello1; R.Rengarajan1; J.Faul1 ; H.Wurzer1; J.Amon1; T.Gaertner2; D.Henke2; M.Schmeide2; A. Kieslich1. i n f i n e o n technologies AG, Memory Products Division, 1Technology Development Dept., 2Unit Processes Dept. – Koenigsbruecker Strasse 180, D-01099 Dresden, Germany. ABSTRACT In this work, we report on the effect of different dual gate oxide (DGox) processes on the electrical properties of CMOS devices in deep submicron embedded DRAM (eDRAM) technology. Also discussed, is the effect of N+ Ion Implantation on the diffusion / segregation behaviour of B and In channel dopants. In particular, it will be shown that the N+ dose required to obtain a certain combination of dual gate oxide thickness varies with the gate oxide process. Effects of N+ dose on the In and B channel profiles are studied using SIMS. The impact of “thickness-equivalent” DGox processes on short channel effect (SCE) and carrier mobility is analyzed and tradeoffs for optimization of device performances are discussed. INTRODUCTION The use of retrograde channel profiles (RCP) for improving SCE in sub quarter micron CMOS technologies is being widely investigated [1, 2]. In addition, lower thermal budget dual gate oxide processes employing selective N+ ion implantation are also being developed in order to integrate high performance CMOS in eDRAM technologies [3]. The impact of nitrogen implantation on retrograde channel profiles and the resulting effect on device electrical properties such as SCE and mobility has not been addressed before and it is the aim of the present work to do so. Indium channel implantation along with low thermal budget gate oxidation processes is normally used to obtain RCP in NFETs. As it will be shown, the nitrogen implant dose required to achieve a certain dual gate oxide thickness ratio increases as the gate oxide thermal budget is reduced. On the other hand, increasing the nitrogen dose results in a broadening of the channel profile, degrading SCE when compared to a device with a RCP. Thus, while lower gate oxide thermal budgets are desiderable to maintain RCP, the lower thermal budgets also necessitate higher nitrogen doses which result in broader channel profiles. Hence a careful optimization of the gate oxide process is required in order to attain the best SCE when combining N+ implant dual gate oxide schemes and RCP. EXPERIMENTAL DETAILS The electrical characterization was performed on support devices of 0.20 and 0.17um eDRAM technologies [4]. These employ single work function, DGox CMOS processes where the PFETs are buried channel devices formed by p-type counterdoping of the N-well and the NFETs are surface channel devices with a B or In channel implant. A masked nitrogen implant was introduced prior to gate oxidation in order to achieve DGox thickness
B3.4.1
2000 MRS Spring Meeting, Symposium B: Si Front-End Processing - Physics and Technology of Dopant-defect Interactions II.
with a single thermal oxidation step. Gate oxides were grown
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