Efficient detection of transistor stuck-on faults in CMOS circuits using low-overhead single-ended ring oscillators
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Efficient detection of transistor stuck‑on faults in CMOS circuits using low‑overhead single‑ended ring oscillators S. M. Ishraqul Huq1 · Apratim Roy1 · Mushfiqul Ahmed2 · Ayman Uddin Mahin2 Received: 13 January 2020 / Accepted: 18 July 2020 © Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract Very large-scale integration technology is accelerating the growth and prevalence of nanoscale devices worldwide, but at the same time facing technical challenges in terms of fault detection due to the compact size of chips. Thus, the detection of faults in chips caused by limitations of the manufacturing process or operational aspects of the architecture is obligatory to assess the effective performance of devices. In this paper, two single-ended ring oscillator (SERO)-based transistor stuckon (TSON) fault detection methods are proposed for complementary metal–oxide–semiconductor (CMOS) circuits. The SERO is used as a current-controlled and voltage-controlled oscillator in method 1 and 2, respectively, reducing the circuit overhead of the detection block. Simulations are carried out using Cadence Virtuoso in 90-nm technology. The results show that both methods can successfully detect TSON faults in CMOS circuits based on the oscillatory behavior of the SERO. Moreover, these methods avoid the need to sense the output voltage level or quiescent current, which increases the possibility of successful fault detection, especially for submicron-level structures by avoiding improper logic and unreliable current values. Test vectors and fault locations can also be easily identified using the proposed methods, reducing the implementation complexity of CMOS fault detection techniques. Keywords CMOS · Stuck-on fault · Single-ended ring oscillator · Voltage-controlled · Current-controlled · Quiescent current
1 Introduction The complementary metal–oxide–semiconductor (CMOS) technology has been dominant over the decades, allowing for the very large-scale integration (VLSI) of complex circuits onto a single chip. The benefits of VLSI circuits are evident, * S. M. Ishraqul Huq [email protected] Apratim Roy [email protected] Mushfiqul Ahmed [email protected] Ayman Uddin Mahin [email protected] 1
Department of Electrical and Electronic Engineering, Bangladesh University of Engineering and Technology, Dhaka, Bangladesh
Department of Electrical and Electronic Engineering, Ahsanullah University of Science and Technology, Dhaka, Bangladesh
2
but the growing complexity of electronic components and systems demands high-quality, simple, and low-cost fault testing to ensure correct operation [1, 2]. Performing such tests has become a difficult and time-consuming task for chips that contain a million or more transistors. The designfor-testability technique is recommended to ease this testing burden. Many such techniques have been proposed, sharing the common aim of trying to reduce the amount of time required to generate test vectors and apply them to the circuit under test (CUT) [3]. Testin
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