Electrical Measurement of the Bandgap of N + and P + SiGe Formed by Ge Ion Implantation
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Abstract N+ and p+ SiGe layers were formed in the source regions of SOI MOSFETs in order to suppress the floating-body effects by means of high-dose Ge implantation. The bandgaps of the layers were evaluated by measuring the temperature dependence of the base current of the source/channel/drain lateral bipolar transistors. It has been found that the reductions of the bandgaps due to the SiGe formation by the Ge implantation were relatively small, compared to those obtained by the theoretical calculation for heavily doped SiGe. It was also found that the bandgap reduction was larger for n+ layers than that for p+ layers. Introduction SOI MOSFETs are attractive candidates for future LSI devices in view of their low power consumption and high-speed performance. However, the floating-body effect is a major obstacle which must be overcome before they can be used in practical applications. This effect causes the lowering of the drain breakdown voltage, anomalous decreases in subthreshold swing and kinks in Id-Vd characteristics [1, 2]. These phenomena are caused by the accumulation of excess carriers generated by the impact ionization near the drain region, in the channel region. In order to suppress these phenomena, the authors have proposed the formation of a narrow bandgap material such as SiGe in the source region and confirmed its effectiveness [3]. We used Ge implantation technique in order to form the SiGe layers[4], considering that in the case of the implantation there is no problem about particles which may be formed during SiGe selective CVD deposition[5]. Applicability of the high current ion implanter for the dopant implantation to this process is another advantage of this technique. Therefore, the bandgap of the n+ and p+ SiGe layers formed by the Ge implantation is an important factor in this technique. In this paper, the bandgaps of the SiGe layers in the source regions were evaluated by measuring the temperature dependences of the base current of the source/channel/drain lateral bipolar transistors. The measurement has revealed that the reductions of the bandgaps due to the SiGe formation by the Ge implantation were relatively small, compared to those obtained by the theoretical calculation for heavily doped SiGe[6]. It has also revealed that the bandgap reduction was larger for n+ layers than that for p+ layers.
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Mat. Res. Soc. Symp. Proc. Vol. 500 ©1998 Materials Research Society
Device Fabrication LOCOS isolations and gate oxide layers with a thickness of 6nm were formed on SOI wafers with a thickness of 90nm. Phosphorous-doped poly-Si gate layers with a thickness of 300nm were then deposited. After the formation of the poly-Si gate electrodes and subsequent oxidation with a thickness of 5nm, Ge implantation was performed. Ge atoms were implanted perpendicular to the surface at 25keV with dosages of 0.5, 1.0 and 3.Ox 1016 cm-2 into source/drain regions. As-implanted Ge profile is shown in ref.[4] for a Ge dosage of 3 x 1016 cm-2. The projected range was about 20nm and the peak Ge concentration w
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