Emerging Materials Challenges in Microelectronics Packaging
- PDF / 324,600 Bytes
- 7 Pages / 612 x 792 pts (letter) Page_size
- 33 Downloads / 254 Views
Emerging Materials Challenges in Microelectronics Packaging D.R. Frear and S.Thomas Introduction The trend for microelectronic devices has historically been, and will continue to be, toward a smaller feature size, faster speeds, more complexity, higher power, and lower cost. The driving force behind these advances has traditionally been microprocessors. With the tremendous growth of wireless telecommunications, rf applications are beginning to drive many areas of microelectronics that traditionally were led by developments in microprocessors. An increasingly dominant factor in rf microelectronics is electronic packaging, and the materials needed to create the package, because the package materials strongly affect the performance of the electronics. Many challenges remain for the packaging of microprocessors as well. These challenges include increased speed, the number of input/output interconnects, decreased pitch, and decreased cost. This article highlights the key issues facing the packaging of high-performance digital and rf electronics. Keywords: electronic materials, flip chips, metals, microelectronics packaging and integration, wire bonding.
Materials Issues in High-Speed Digital Packaging The ability to decrease line width and feature size in semiconductor technology is now approaching the sub-90-nm level. As the feature size shrinks, the function per unit area on a die increases. This increased functionality means either smaller die or more input/output (I/O) interconnects per die. A reduced die size also reduces the available perimeter for wirebond pads, while increased functionality requires more I/O interconnects. As the die shrinks in size, the decreased perimeter area on the die results in a finer pitch between bond pads, so the capability for wire-bonding the interconnects must decrease to a 44-m pitch with 1.0-m gold wire. An attractive solution to the challenges presented by this decreasing size is to use the entire surface of the chip (i.e., a flip chip), rather than just the periphery. A flip-chip interconnect is a packaging technology in which wire-bonded interconnects on the perimeter are replaced
68
with solder balls deposited on top of the die; the die is then flipped over and soldered directly to the substrate interconnects. Figure 1 shows a comparison of available I/O interconnects for a given die size for standard and state-of-the-art wirebond and flip-chip pitches. From an overall digital package perspective, the trend is moving from perimeterbonded die and packages, to array packages, and then to array die bonds in an array package that offers a greater number of I/O interconnects and increased performance potential. This trend is shown in Figure 2. Materials used in the package and substrate (e.g., ceramic, such as Al2O3; low-temperature cofired ceramic, LTCC; and organic laminates) and package style affect performance as well as area array versus peripheral interconnects. Ceramic packages are the material of choice for hermetic high-performance applications. Ceramic is typically 9
Data Loading...
