A Self-Aligned Silicide Process for Thin Silicon-on-Insulator MOSFETs and Bulk MOSFETs with Shallow Junctions
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A self-aligned silicide process for thin silicon-on-insulator MOSFETs and bulk MOSFETs with shallow junctions G. M. Cohen, C. Cabral, Jr., C. Lavoie, P. M. Solomon, K.W. Guarini, K.K. Chan, R.A. Roy IBM T. J. Watson Research Center, Yorktown Heights, NY 10598 Abstract: We discuss a modified self-aligned silicide (salicide) process that uses a silicon cap to reduce the substrate silicon consumption by 50% as compared with a conventional salicide process. We have used a metal-silicon mixture to form the metal-rich phase reliably in the first anneal. After etching the unreacted mixture we deposit a silicon cap. This forces the metal to react with the silicon cap as well as with the substrate during the second anneal, thus minimizing silicon consumption from the substrate. The unreacted portion of the silicon cap is selectively etched, leaving a structure with a raised source and drain. We expect this process to be useful for forming silicide on shallow junctions and thin SOI films, where silicon consumption is constrained. Introduction: Self-aligned silicide (salicide) is an integral process in the fabrication of highperformance CMOS devices. The salicide process converts the surface portions of the source, drain, and gate silicon regions into a silicide. Due to the low sheet resistance of the silicide film, the series resistance to the intrinsic device is minimized. In bulk devices the silicide film must be contained within the source and drain junction or otherwise it would form a leakage path to the substrate. Moreover, to obtain a good ohmic contact it is desirable to target the silicide/silicon junction to coincide with the peak concentration of the source/drain doping. Scaling the gate length of a MOSFET requires shallow junctions to suppress short channel effects (SCE) [1,2]. The junction depth is expected to become comparable or even thinner than the required silicide film thickness. Meeting the shallow junction requirement and maintaining a thick enough silicide film requires a revision of the conventional salicide process. Scaling of the silicon-on-insulator (SOI) MOSFET leads to similar constraints on the salicide process. In the case of SOI, reducing the channel thickness (tsi) has been found to suppress SCE for both single-gate and double-gate MOSFETs [1]. The use of the conventional salicide process with devices having a very thin SOI channel leads to the following problem: There may not be enough silicon in the source/drain regions to complete the silicide formation. However, even consumption of more than 80% of the silicon film would actually increase the series resistance due to a reduction in the contact area [3]. Constraints on the silicon consumption by silicide imposed by future bulk and SOI technologies require altering the conventional salicide process to be compatible with ultra shallow junction technology and ultra thin SOI films. In this paper we describe a modified salicide process which reduces the silicon consumption from the substrate by 50%. The process is thus most suitable for making si
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