Epitaxial and Non-Epitaxial Heterogeneous Integration Technologies at NGST
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1068-C02-02
Epitaxial and Non-Epitaxial Heterogeneous Integration Technologies at NGST Augusto Gutierrez-Aitken, Patty Chang-Chien, Bert Oyama, Kelly Tornquist, Khanh Thai, Dennis Scott, Rajinder Sandhu, Joe Zhou, Peter Nam, and Wen Phan Northrop Grumman Space Technology, Redondo Beach, CA, 90278 Introduction Present systems requirements are increasingly challenging and complex and this trend is likely to increase rapidly for future systems. This translates into more demanding electronic functions to support these needs and higher performance of the microelectronic technology in which these functions are implemented. There are increased requirements in all aspects of the technology capability such as increased speed, bandwidth, output power, gain, and reduced size, weight and power (SWAP), and also cost and fabrication cycle time. To meet these requirements, it is not enough to use one single semiconductor technology but to combine or integrate several high performance technologies in an efficient and cost effective way. In some cases this involves the integration of semiconductor technologies based on different substrates and in other cases it involves the integration of two types of devices on the same substrate. The combination of two or more dissimilar microelectronic technologies, or heterogeneous integration, leads to a significant higher design flexibility and performance and lower SWAP There are several approaches to perform this heterogeneous integration. In this paper we describe some of the heterogeneous integration approaches that are being used and developed at Northrop Grumman Space Technology (NGST) that include selective epitaxial growth, metamorphic growth and wafer level packaging (WLP) technology (Figure 1). More recently we are developing a scaled and selective wafer packaging technique to integrate III-V semiconductors with silicon under the Compound Semiconductor Materials on Silicon (COSMOS) Defense Advanced Research Projects Agency (DARPA) program. The integration of compound semiconductors with Silicon adds a new level of complexity due to the significantly different fabrication processes, thermal budgets, wafer sizes and integration scales, but promises an unparalleled capability based on the very high performance of the III-V technology and the large scale integration level of the Si technology. Wafer 2 Device with lattice constant N
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Figure 1. Heterogeneous integration methods used or being developed at NGST. (a) Selective epitaxy, (b) metamorphic growth and (c) wafer level packaging
Selective Epitaxial Heterogeneous Integration In the selective epitaxy heterogeneous integration technique (Figure 1a), two or more different types of devices are monolithically integrated on one substrate. At NGST, typically these devises are high electron mobility transistors (HEMT’s) and heterojunction bipolar transistors (HBT’s). HEMT devi
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