Ferroelectric Gate FET Memory based on Conduction of SBT-SiON Interface
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0966-T13-06
Ferroelectric Gate FET Memory based on Conduction of SBT-SiON Interface Masanori Okuyama, Takaaki Minami, Bong-Yeon Lee, and Takeshi Kanashima Department of Systems Innovation, Graduate School of Engineering Science, Osaka University, 1-3 Machikaneyama-cho, Toyonaka City,Osaka, 560-8531, Japan
ABSTRACT A new type of ferroelectric gate field-effect transistor (FET) using ferroelectric-insulator interface conduction has been proposed. Drain current flows along the interface between the ferroelectric and insulator layers and requires no semiconductor. This FET is fabricated by forming of source and drain electrodes on a SiON/Si substrate, dpositing SrBi2Ta2O9(SBT) film, forming topgate electrode, and forming bottom electrode. Drain current versus topgate voltage characteristics show a clockwise hysteresis loop similarly to the conventional metal-ferroelectricinsulator-semiconductor-FET(MFIS-FET). This FET shows that the On/Off ratio of the drain current is 104 to 105 and the Off state current of about 10-9 A. INTRODUCTION Recently, ferroelectric random access memories (FeRAMs) have attracted much attention as they have prominent merits such as nonvolatile memory, fast response and low power consumption. These memories are categorized mainly in two kinds; the one-transistor onecapacitor (1T1C) type and the ferroelectric gate field effect transistor (FET) (one-transistor (1T) type) [1]. In principle, the 1T-type FeRAM shows good scalability and nondestructive read-out operation, can increase the integration level to be higher than that of the conventional 1T1C-type FeRAM, and so the 1T-type FeRAM is superior to the 1T1C-type memory. However it has short memory retention time at present, regardless of some exceptions in recent successful studies [26]. The reasons for the short retention have been discussed for long time, [7,8] and it is attributed to electronic property of the ferroelectric and insulator of the MFIS-FET gate structure. Important factors limiting the retention time are the existence of a depolarization field in the ferroelectric layers and leakage current through the MFIS structure over the current channel. To solve this situation, one idea is to explore a new principle of ferroelectric transistor with nonvolatile memory operation, which does not suffer from damage due to mutual diffusion at the channel region, and/or has the other operation mechanism more directly related with the ferroelectric polarization reversal then not sensitive to the leakage and the depolarization field. For example, it is a structure using the conduction between the ferroelectric and insulator layer. This structure does not need a Si substrate. So, it is free of damage brought about by mutual diffusion between the ferroelectric film and Si surface channel region. And the principle of operation is more directly related to a ferroelectric polarization reversal which is insensitive to the leakage current and the depolarization field. The depolarization field in the ferroelectric has been reduced significantly because c
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