Performance Analysis of Gate Electrode Work Function Variations in Double-gate Junctionless FET
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ORIGINAL PAPER
Performance Analysis of Gate Electrode Work Function Variations in Double-gate Junctionless FET Sandeep Kumar 1 & Arun Kumar Chatterjee 1 & Rishikesh Pandey 1 Received: 27 June 2020 / Accepted: 12 October 2020 # Springer Nature B.V. 2020
Abstract With inherent structural simplicity due to the omission of ultrasteep p-n junctions, the conventional junctionless FET can be used as a barrier-controlled device with low OFF-current in the nanoscale regime. In this work, numerous performance parameters of conventional double-gate junctionless FET namely threshold voltage, OFF-current, ON-current, ON-to-OFF current ratio, and subthreshold slope have been investigated for the range of gate work function from 4.6 eV to 5.6 eV. The performance of conventional double-gate junctionless FET has been further improved with the proposed recessed double-gate junctionless FET using recessed silicon film in the channel region and it has been found that for the gate work function of 5.1 eV (mid-value) the proposed device shows OFF-current of the order of ~ 10− 14 A/µm, ON-to-OFF current ratio of the order of 1010 and subthreshold slope of 65.6 mV/dec as compared to the conventional double-gate junctionless FET. Interestingly, a range of work function values have been found to obtain the optimum performance from the conventional and proposed recessed double-gate junctionless FETs for low power applications. In the work function window, the variations in transconductance and gate-tosource capacitance for both junctionless devices have been illustrated. The impact of different values of the work function of the two gate electrodes for both junctionless devices has also been presented and it is found that the proposed device reflects robustness with nearly constant subthreshold slope. Keywords Work function . MOSFET . Double-gate . Junctionless FET . OFF-current
1 Introduction In the era of artificial intelligence (AI) and the internet of things (IoT), Moore’s law will be driven with innovations in the area of monolithic scaling and system scaling. With a focus on transistor size miniaturization and reduction of operating voltages, the monolithic scaling results in improved device performance [1]. One such advancement in the area of monolithic scaling has been reported with the realization of the transistor without junctions, called junctionless fieldeffect-transistor (JLFET) [2]. The device consists of a
* Sandeep Kumar [email protected] * Arun Kumar Chatterjee [email protected] * Rishikesh Pandey [email protected] 1
Department of Electronics and Communication Engineering, Thapar Institute of Engineering & Technology, Patiala, Punjab, India
uniformly heavily doped silicon film from the source through the channel to the drain region. The non-requirement of ion implantation step to create the source/drain region, absence of inversion mode in the drain current vs. gate-to-source voltage characteristics (ID-VGS), zero vertical electric field in ONstate, and bulk conduction mechanism differentiate the juncti
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