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0997-I03-02

Memory window in ferroelectric PVDF copolymer gate integrated MOSFET devices for nondestructive readout memory application Sang-Hyun Lim, Alok C Rastogi, and Seshu B Desu Electrical and Computer Engineering, University of Massachusetts, Amherst, MA, 01003 ABSTRACT Metal-Ferroelectric-Oxide-Si (MFEOS) field effect transistor (FET) with ferroelectric polyvinylidene fluoride trifluoroethylene copolymer (PVDF-TrFE) gate for nonvolatile memory application is demonstrated. Memory window ascribed to the ferroelectric polarization switching and quantified by the shift of threshold voltage is in the 4-5 V range. Non saturating IDS is due to free ionic polarization field. IDS-VDS characteristics of functional FET are realized after AC poling. INTRODUCTION Nonvolatile ferroelectric memories with non destructive read out functionality have been realized by integrating ceramic ferroelectric film directly over the gate channel of a Si -FET. The one transistor (1-T) memory structure referred to as MFEOS-FET device has highest integration density. Data is stored as a conducting channel is formed between source and drain (ON-state) when voltage is applied to the gate through the word line. Data is retained as induced remnant polarization at ferroelectric gate continues to hold the channel after gate voltage is withdrawn. Data can be read repeatedly by sensing channel current at low bias. Integration of oxide ferroelectrics on Si beset with interdiffusion and varied ferroelectric film composition problems require interface barrier layers [1,2]. High depolarization field encountered in ferroelectric and barrier bilayer gate stacks and leakage current at the gate are detrimental to data retention [3]. Further, carrier trapping at interface defects and localized charge compensation interferes in optimizing polarization and sustaining threshold voltages. Several successful 1-T memory device studies have been reported which have dealt the problem by using low dielectric constant ferroelectric oxide films [4,5], buffer layers [6], novel device structures [7,8] and integration, schemes [5,7]. Polymeric ferroelectric with low dielectric constant and low temperature process ability appear attractive for 1-T memory devices. Recently we have reported [9] MFEOS capacitor devices based on polyvinylidene fluoride (PVDF) copolymer with trifluoroethylene (TrFE) ferroelectric film and showed that Si surface potential can be varied by polarization state. In this paper we report on the MFEOS-FET device based on (PVDF-TrFE)-SiO2 buffer gate stack and explore its potential for 1-T memory use. EXPERIMENTAL P-channel MOSFET with 20 µm gate length and 80 µm width was fabricated by standard Si microfabrication process. Ferroelectric PVDF 450 nm thin film was integrated on oxide gate by spin casting and lithography. Its ferroelectric properties were optimized by annealing at 145∫C for 45min and by DC poling. Gate contact was made by 150 nm thick evaporated Ti film. RESULTS AND DISCUSSION

Crystalline structure and morphology of ferroelectric PVD