Germanium & Carbon Co-implantation for Enhanced Short Channel Effect Control in PMOS Devices
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0912-C01-05
Germanium & Carbon Co-implantation for Enhanced Short Channel Effect Control in PMOS Devices Benjamin Dumont1,2, Arnaud Pouydebasque3, Bartek Pawlak4, Benjamin Oudet1, Dominique Delille3, Frederic Milesi5,6, Kader Souifi2, and Thomas Skotnicki1 1 STMicroelectronics, 850 rue Jean-Monnet, Crolles, 38920, France 2 LPM - INSA de Lyon, Bât. Blaise Pascal, 7, avenue Jean Capelle, Villeurbanne, 69621, France 3 Philips Semiconductors, 850 rue Jean-Monnet, Crolles, 38926, France 4 Philips Research, Kapeldreef 75, B-3001, Leuven, Belgium 5 Ion Beam Services, ZI Peynier-Rousset, rue Gaston Imbert prolongée, Peynier, 13790, France 6 CEA-LETI, 17 rue des Martyrs, Grenoble, 38000, France ABSTRACT This work demonstrates the efficiency of a Germanium and Carbon co-implantation that suppresses the Boron Transient Enhanced Diffusion, enhances Boron activation and enables large improvement of Short Channel Effects in PMOS devices while maintaining drive current performances. We present here 65/45nm node devices on conventional bulk substrates featuring Germanium and Carbon engineered shallow junctions that enable to reduce the Drain Induced Barrier Lowering compared to devices implanted only with Boron. This improvement is attributed to the suppression of Boron channelling with Ge pre-amorphization (PAI), and to the reduction of Boron TED due to the trapping of interstitial defects by Carbon with Germanium PAI. INTRODUCTION Parasitic phenomena like Short Channel Effects (SCE) and Source/Drain Extension (SDE) resistances become critical parameters for the 65nm node and below. To control SCE, the most promising studies deal with high temperature-short time scale annealing such as Laser or Flash anneals, which were proven to stop the diffusion of the dopants keeping a good electrical activation [1,2]. However, these techniques require a specific tool and the ultra-high temperatures used may render problematic the introduction of new technological boosters such as high-K dielectrics, metal gates or process induced strain. We propose here a simpler alternative by the use of Germanium and Carbon co-implantation in PMOS device SDE. Fundamental studies have shown that Carbon acts as a trap for Si self-interstitials that suppresses the Boron Transient Enhanced Diffusion (TED) [3,4,5,6]. Thus, by the mean of SiGe:C epitaxy, Heterojunction Bipolar Transistors (HBT) applications [7] and Si MOSFETs applications [8] were considered. In this work we demonstrate for the first time the usefulness of Germanium and Carbon co-implantation with a standard spike anneal to control Boron TED in order to improve PMOS device characteristics.
PRELIMINARY STUDY Fig.1 shows SIMS profile of Boron implanted with Ultra Low Energy and PAI+Carbon+Boron and annealed with a spike RTP. With PAI+C+B, the junction depth Xj can be reduced by 40% with an impressive abruptness at the resolution limit of the SIMS. As shown in Fig.2, the Sheet Resistance (Rs)/Junction Depth (Xj) trade-off is drastically improved with PAI+C+B and can fulfil the ITRS specifications
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