Grinding and Mixed Silicon Copper CMP of Stacked Patterned Wafers for 3D Integration
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0970-Y06-03
Grinding and Mixed Silicon Copper CMP of Stacked Patterned Wafers for 3D Integration Koen De Munck, Jan Vaes, Lieve Bogaerts, Piet De Moor, Chris Van Hoof, and Bart Swinnen IMEC, Kapeldreef 75, Heverlee, 3001, Belgium
ABSTRACT 3D integration promises to reduce system form factor through direct stacking and interconnection of chips made using different technologies, into a single system. In our case, these interconnects consist of small and deep through wafer vias in the form of Cu nails. One of the enabling technologies to achieve 3D stacks, is thinning on carrier. It involves backside grinding and CMP of patterned wafers down to 20 micron, while temporarily glued to a carrier. Success of grinding on carrier is found to strongly depend on temporary glue layer properties and bonding quality. Voids in between device wafer and carrier of various origins were observed to cause thin wafer delamination and catastrophic breakage when grinding down below 50 micron. By improvements in the bonding process, we eventually enabled uniform bonding, compatible with standard grinding and CMP techniques. CMP both removes grinding-induced damage and exposes the Cu nails at the thin wafer backside. The developed CMP consists of 2 steps which are optimized to reduce Cu smearing and within-die uniformity. Both are found to correlate with the local Cu nail density variations. INTRODUCTION Three dimensional (3D) interconnect schemes are gaining interest in order to meet the scaling, performance and functionality requirements of the technology roadmap [1]. One option to 3D integration, which is pursued at IMEC, is the 3D-Stacked IC approach (3D-SIC) [2]. In this approach a “Cu nail” is realized immediately after FEOL processing as the first part of the BEOL, using a modified Cu-damascene process. Carrier wafer ~ 700 µm Glue layer ~3-10 µm
a)
b)
Device wafer ~700 µm Glue layer deposition and wafer bonding
f)
c) Thinning wafers by CMP
Thinning wafers by grinding
e)
d) Recess etching of Cu nails
Carrier removal
Cu-Cu bonding (die level)
Figure 1: Schematic representation of the mounting, thinning and bonding as a part of the 3DSIC approach to enable 3D integration. Only the Cu-Cu bonding is done at die level.
Typical Cu nails have a diameter of 3 to 5µm, with an aspect ratio of 5 to 10 and are isolated from the silicon by a TEOS liner (Tetra Ethyl OrthoSilicate). After completion of back-end processing, the wafer is temporarily glued with its frontside to a carrier wafer (Figure 1a) [3]. Backside grinding (Figure 1b) reduces the device wafer thickness down to 20 to 30 µm without exposing the Cu nails. CMP removes any grinding induced damage and exposes the Cu nails (Figure 1c). As such, nail length variations associated with via etch non-uniformity and glue, carrier and grinding TTV’s (Total Thickness Variation) are flattened out. A selective silicon etch recesses the silicon compared to the Cu nails (Figure 1d). Following dicing, the dies are stacked using Cu-Cu thermal compression bonding, creating vertical interc
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