• PDF / 2,378,782 Bytes
• 8 Pages / 612 x 792 pts (letter) Page_size
• 77 Downloads / 216 Views

DOWNLOAD

REPORT

---

0970-Y06-02

Through-Silicon-Via Copper Deposition for Vertical Chip Integration Bioh Kim ECD Division, Semitool, Inc., 655 West Reserve Drive, Kalispell, MT, 59901 ABSTRACT Through-silicon-via (TSV) interconnection can provide the shortest and most plentiful connections with reduced signal delay and power consumption. Void-free copper filling within high aspect ratio vias is one of the key technologies to make TSV chip integration manufacturable and reliable. After investigating the impacts of varying deposition conditions on the copper filling within high aspect ratio vias, we found that reducing current crowding at the via mouth and mass transfer limitations at the via bottom is critical in achieving a superconformal filling profile. This condition can be achieved only with a proper combination of seed conformality, surface wettability, bath composition, waveform, current density, and flow conditions. We reduce the current crowding at the via mouth and improve bottom-up filling either with pulse reverse (PR) waveform or with chemical composition (which has a strong organic function such as leveling, suppression, and acceleration). PR waveforms with proper waveform parameters are helpful for reducing overhang and assisting bottom-up filling especially within high aspect ratio, deep vias. Reducing mass transfer limitations at the via bottom is achieved with a high limiting-current-density (LCD) bath and strong flow mechanism. With increasing average current density and all other process variables fixed, deposit profiles change significantly, which leads to higher tendency of overhang at the via mouth. This is attributed to more current crowding at the via mouth and more severe mass-transfer limitations at the via bottom at a higher current density. With optimized deposition conditions, we demonstrated void-free, bottom-up filling with a variety of via dimensions (3-80µm wide and 25-160µm deep vias) in 150mm and 200mm wafers. INTRODUCTION The continuous pressure to reduce size, weight, and cost, while increasing the functionality of portable products, has led to innovative 3D packaging concepts. The general advantages of 3D packaging include the miniaturization of size and weight, the integration of heterogeneous technologies in a single package, the replacement of long 2D interconnects with short vertical 3D interconnects, and the reduction of parasitics and power consumption. Therefore, 3D packaging can offer significant advantages in performance, functionality, and form factor. Among all kinds of 3D packaging techniques, TSV electrodes can provide the shortest and most plentiful connections with a variety of benefits [1-3]. Connection lengths can be as short as the thickness of a chip, which has the potential to significantly reduce the average wire length of block-toblock interconnects by stacking logic blocks vertically. High-density, high-aspect-ratio connections are possible, which allows implanting complex, multi-chip systems entirely within silicon with a physical packing density many times better than toda