Growth and In-line Characterization of Silicon Nanodots Integrated in Discrete Charge Trapping Non-volatile Memories
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Growth and In-line Characterization of Silicon Nanodots Integrated in Discrete Charge Trapping Non-volatile Memories J. Amouroux 1,2,3, V. Della Marca 1,2,3, E. Petit 1,2 , D. Deleruyelle 2 , M. Putero 2, Ch. Muller 2, P. Boivin 1, E. Jalaguier 3, J-P. Colonna ³, P. Maillot 1, and L. Fares 1 1
STMicroelectronics, 190 Avenue Célestin Coq, F-13106 Rousset Cedex, France.
2
Im2np, Institut Matériaux Microélectronique et Nanosciences de Provence, Aix-Marseille Université, Avenue Escadrille Normandie Niemen, F-13397 Marseille Cedex 20, France. 3
CEA LETI/MINATEC, 17 Rue des Martyrs, F-38054 Grenoble Cedex, France.
ABSTRACT Non-Volatile Memories (NVM) integrating silicon nanodots (noted SDs) are considered as an emerging solution to extend Flash memories downscaling. In this alternative memory technology, silicon nanocrystals act as discrete traps for injected charges. Si-dots were grown by Low Pressure Chemical Vapor Deposition (LPCVD) on top of tunnel oxide. Depending on the pre-growth surface treatment, tunnel oxide surface may present either siloxane or silanol groups. SDs deposition relies on a 2–steps process: nucleation by SiH4 and selective growth with SiH2Cl2. In a context of technological industrialization, it is of primary importance to develop in-line metrology tools dedicated to Si-dots growth process control. Hence, silicon-dots were observed in top view by using an in-line Critical Dimension Scanning Electron Microscopy CDSEM and their average size and density were extracted from image processing. In addition, Haze measurement, generally used for bare silicon surface characterization, was customized to quantify Si-dots deposition uniformity over the wafer. Finally, Haze value was correlated to Si nanodots density and size determined by CDSEM. INTRODUCTION Non-Volatile Memories integrating silicon nanodots are considered as an emerging solution for extending Flash memories downscaling. Si-dots are used as discrete traps for injected charges in replacement of the conventional polycrystalline silicon floating gate. For illustration, Fig. 1 shows transmission electron microscopy (TEM) cross sections of Flash cells with either continuous polysilicon floating gate (Fig. 1a) or discrete gate with Si-nanodots (Fig. 1b). Silicon nanodots integration enables improving reliability performances in terms of endurance and retention. Besides, the robustness to parasitic cross-talk is enhanced and the sensitivity to defects within tunnel oxide is lowered since Si-dots are isolated from each other [1]. Si-nanodots integration is fully compatible with CMOS process and fabrication tools [2]. Since SDs with diameter around 10 nm cover a drastically smaller area than a continuous polysilicon gate, a downscaling toward more aggressive technological node is expected [3,4]. Finally, the lower number of photolithography masks leads to a reduction in wafer cost [5]. This paper shows how silicon nanodots were integrated in Flash-like non-volatile memory cells and describes various in-line and off-line metrology tools dedicated to
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