High mobility germanium-on-insulator p-channel FinFETs
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. LETTER .
April 2021, Vol. 64 149402:1–149402:2 https://doi.org/10.1007/s11432-019-2846-9
High mobility germanium-on-insulator p-channel FinFETs Huan LIU, Genquan HAN* , Jiuren ZHOU* , Yan LIU & Yue HAO State Key Discipline Laboratory of Wide Band Gap Semiconductor Technology, School of Microelectronics, Xidian University, Xi’an 710071, China Received 14 October 2019/Revised 4 February 2020/Accepted 18 March 2020/Published online 25 November 2020
Citation Liu H, Han G Q, Zhou J R, et al. High mobility germanium-on-insulator p-channel FinFETs. Sci China Inf Sci, 2021, 64(4): 149402, https://doi.org/10.1007/s11432-019-2846-9
Dear editor, Over the past decade, germanium has attracted great interest as a promising channel material for p-channel metal oxide semiconductor field-effect-transistor (MOSFET), owing to its higher hole mobility over Si [1]. Tremendous efforts were devoted to solving the technical issues for its practical applications, including source/drain (S/D) ohmic contact formation, strain engineering, channel surface passivation, and gate dielectric engineering [2]. In particular, it is reported that the the effective hole mobility (µeff ) of Ge pMOSFET can be effectively enhanced by the reduced density of interface trap via gate dielectric engineering [3]. ZrO2 , one of the most promising dielectric materials [4,5], demonstrates both excellent dielectric properties and ferroelectricity, which play a critical role for future CMOS technology in ‘More than Moore’ era [6]. Studies have shown that a GeO2 interfacial layer can decompose and intermix with the ZrO2 layer during thermal annealing, decreasing CET [7]. However, there is still a lack of experimental investigation on Ge p-channel FinFETs with ZrO2 dielectric. In this study, Ge p-channel FinFETs with ZrO2 dielectric are fabricated on (100)-oriented germanium-on-insulator (GeOI), which demonstrates the improved µeff compared to Si universal mobility. The impacts of fin direction on the electrical performance of the devices are also discussed. Device fabrication. GeOI wafer with 100 nm top Ge(100) film and ∼150 nm buried oxide is used for the FinFET fabrication. A phosphorous ion (P+ ) implantation with a dose of 1 × 1013 cm−2 and an energy of 45 keV is carried out, followed by the thermal annealing at 700◦ C to form the nwell. And then, S/D regions were defined and implanted 15 cm−2 and an energy of using BF+ 2 with a dose of 1 × 10 30 keV. After that, dry etching is used to reduce the top Ge to about 50 nm. Fins are formed by the patterning using e-beam lithography and dry etching. After a pre-gate cleaning, the wafers are loaded into an atomic layer deposition chamber for the formation of the 4.5 nm ZrO2 gate dielectric layer at 300◦ C. Zr[N(CH3 )2 ]4 and H2 O are used as the precursors of Zr and O, respectively. During deposition, the Zr[N(CH3 )2 ]4 source is heated to 85◦ C. Subsequently,
a TaN gate layer is deposited. After this layer is patterned to form the gate electrodes, Nickel S/D metal electrodes are then formed by a lift-off process
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