Novel contact structures for high mobility channel materials
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oduction As we reach the end of the silicon technology roadmap, alternative materials such as high mobility Ge1,2 and III–Vcompounds3–5 have proven to be strong contenders for extending high performance logic beyond the 22 nm technology node. However, before these technologies can be implemented, a few of the existing problems must be solved. These include the gate dielectric to channel interface, integration on silicon, a smaller device footprint in line with the device density improvement expected of each successive technology node, and low-resistance source/drain contacts, where the latter is related to the formation of Schottky barriers. In the case of Ge metal oxide semiconductor field-effect transistors (MOSFETs), high-performing pMOSFETs have already been demonstrated, but Ge nMOSFETs still have much room for improvement. Ge nMOSFET performance is currently limited by high interface trap density at the gate dielectric, which causes inversion charge loss through trapping,1 and large source/drain (S/D) parasitic resistance (RSD), which results in the measured extrinsic performance falling far behind the intrinsic performance. The high RSD is a combined result of low n-type dopant solubility and Fermi-level pinning in the source/drain regions. Strong Fermi-level pinning at the metal/semiconductor
interface is observed when metal work functions are varied from 2.8 eV (Ce) to 5.6 eV (Pt), but the Schottky barrier height was found to only vary from 0.49 to 0.64 eV.6 The roughly 0.5 eV barrier height is also far from the near zero barrier needed for good ohmic contacts. Recent work on sulfur-passivated Ni germanide contacts to n-Ge has demonstrated barriers as low as 0.15 eV,7 which is promising, but the current-voltage characteristics remain rectifying. For III–V compound semiconductors, Fermi-level pinning also results in high Schottky barrier heights, and in materials with large bandgaps such as GaAs (1.42 eV), the pinned barrier can be fairly large, ranging from 0.7 to 1.0 eV.8 Without the silicidation technology available to Si and the germanide technology for Ge, III–V materials rely on multilayered alloyed structures to form ohmic contacts (for example Au/Ge/Ni in the case of GaAs). These S/D contact materials can then diffuse up to hundreds of nanometers during alloying, so in order to prevent electrical shorting, most promising III–V FET/high-electron-mobility transistors (HEMTs) demonstrated have S/D spacings in the micron scale, despite nanometer scale gate lengths. In recent work on non-alloyed contacts to HEMTs, Waldron et al.9 had a 60 nm contact-to-gate separation using W to contact In0.65Ga0.35As with a doping density of 2 × 1019 cm–3.
Jenny Hu, Stanford University; [email protected] H.-S. Philip Wong, Stanford University Krishna Saraswat, Stanford University; [email protected] DOI: 10.1557/mrs.2011.5
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MRS BULLETIN • VOLUME 36 • FEBRUARY 2011 • www.mrs.org/bulletin
© 2011 Materials Research Society
NOVEL CONTACT STRUCTURES FOR HIGH MOBILITY CHANNEL MATERIALS
Singisetti et al.10 achiev
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