High Speed Low Power Implementation of Combinational and Sequential Circuits Using Reversible Logic
In this paper a survey on design options is carried out. An investigation of comparative analysis of 1-bit full adder with various options on the basis of power dissipation, propagation delay, and area concerning to the of number of transistors used, Ener
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Abstract. In this paper a survey on design options is carried out. An investigation of comparative analysis of 1-bit full adder with various options on the basis of power dissipation, propagation delay, and area concerning to the of number of transistors used, Energy Delay Product (EDP) & Power Delay Product (PDP). In present scenario, reversible logic based designing is attracting researchers because of its less power usage. Reversible logic is playing important role in low-power circuit scheme. The application areas of reversible logic is nanotechnology, CMOS(less power), cryptography, DSP, DNA & quantum computing, communication, computer graphics. To contract quantity price, the profundity of circuits & count of drivel outputs are the main aim of intending reversible logics gates. This work will give brief idea about building of full adder circuits using the basic reversible gates. Keywords: Reversible logic Power dissipation Propagation delay Energy delay product and power delay product
1 Introduction VLSI Circuit design has gain interest in the past few decades and substantial growth is done in the development of this. As the Application Specific architectures & microprocessors comprises many components needed big rooms in the 70’s, but the present scenario is that too many transistors are built up on about square millimeters. These are the results of the accomplishments made in the world of semiconductors based on Moore’s law. Still, it’s apparent that such extensive development will attain its boundaries in the future when the shrinking attains a level, whereas single transistor sizes are approaching the nuclear scale. Because of this, few researchers anticipate that from the 2020 about, germination of transistor density won’t be potential anymore. Furthermore to meet the demands for extra computational power, alternatives are demanded that go outside the range of conventional technologies such as CMOS. Several design options are available in order to achieve the low power high speed VLSI circuits & the design target of any such circuit includes high speed, low power consumption, less area or a combination of any of the above & is a wide topic of research. © Springer Nature Singapore Pte Ltd. 2016 A. Unal et al. (Eds.): SmartCom 2016, CCIS 628, pp. 743–751, 2016. DOI: 10.1007/978-981-10-3433-6_89
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S. Keshkamat and S.T. Gandhe
The power dissipation & thereupon heat generation is a crucial problem for system architecture & energy dissipation is because of the un-ideal nature of transistors & materials. The work is divided in two phases as survey of work done on the design options of a 1-bit Full Adder & implementation of the same by using reversible logic for efficient performance. The first phase presents a detailed survey about the design options for performance efficiency of VLSI designs so as to build up in low power & high speed. The physical & geometrical parameters have been studied along with various logic techniques proposed till the date. The phase two of the presented work consist of the a
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