Hot Carrier Effects in Self-aligned and Offset-Gated Polysilicon Thin-Film Transistors
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Hot Carrier Effects in Self-aligned and Offset-Gated Polysilicon Thin-Film Transistors N. Arpatzanis1, A. T. Hatzopoulos1, D. H. Tassis1, C. A. Dimitriadis1 and G. Kamarinos2 1 2
Department of Physics, Aristotle University of Thessaloniki, 54124 Thessaloniki, Greece IMEP ENSERG, 23 rue des Martyrs, BP 257, 38016 Grenoble Cedex 1, France
ABSTRACT The effects of hot carriers on the transfer characteristics of self-aligned and offset-gated polysilicon thin-film transistors (TFTs), with channel length L = 10 μm and offset length ΔL = 2 μm, are investigated. In the self-aligned device, the on-state current is substantially reduced, whereas the subthreshold slope remains almost unaffected. In the offset gated device, the transfer characteristic is shifted first positively and then negatively, the on-state current is still substantially reduced and well-defined kinks are formed in the subthreshold region. The device degradation is found to become more pronounced in the offset gated device. A model explaining the post-stress performance of the offset-gated device is presented.
INTRODUCTION Polysilicon thin-film transistors (TFTs) have been widely used for applications in activematrix liquid-crystal displays and three-dimensional integrated circuits [1]. For such applications, hot-carrier induced instability is one of the major problems of the polysilicon TFTs. It has been pointed out that the instability of polysilicon TFTs is more serious than that of singlecrystalline silicon MOSFETs, associated with the high density of defects which enhance the local electric field near the drain region and with the poor polysilicon/oxide interface quality [2]. In order to suppress hot carrier effects in polysilicon TFTs, devices with different drain junction architectures were used to reduce the electric field near the drain. For this purpose, lightly doped drain (LDD) and gate overlapped lightly doped drain (GOLLD) structures were used [3]. Biasstress experiments have demonstrated that the electrical stability of LDD structures remains still poor compared to the self-aligned devices, whereas GOLLD devices are characterized by a very high electrical stability. Recently, intrinsic offset gated structures were used to reduce the fabrication cost of the LDD polysilicon TFTs. By using intrinsic polysilicon of high quality and with a proper combination of the channel and offset lengths, the leakage current is effectively suppressed without degrading seriously the on-current [4]. In this work, we investigate the effects of hot carriers on the performance of intrinsic self-aligned n-channel polysilicon TFTs with channel length L = 10 μm and similar offset gated devices with offset length ΔL = 2 μm. From the evolution of the transfer characteristics during electrical stressing, the transistor aging is deduced. EXPERIMENTAL DETAILS The investigated devices were fabricated on fused quartz glass substrates, covered by 200 nm thick SiO2, with the standard low temperature process. The active polysilicon layers (50 nm
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