Implantation Induced Charge Trapping and Interface States Generation in Si-SiO 2 System
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H. WONG and N.W. CHEUNG Department of Electrical Engineering and Computer Sciences, University of California, Berkeley CA 94720
ABSTRACT
Constant-voltage stressing has been used to investigate the damage of Si0 2 and the Si/Si0 2 interface induced by silicon implantation through polysilicon/SiO 2/p-Si structures annealed at 950 0 C. The implant doses used were from 5x×10'cm-2 to t0' 4cm-2. Although no detectable interface states density was observed after the annealing for implant doses less than 2x 1013cm-2, interface states generation, hole trapping, and electron trapping were found to be greatly enhanced by the Si implantation. The interface states density generation rate was found to increase with higher implant doses. The density of hole trapping centers saturated at a value of 3x 10' 2cm-2 for implant doses higher than 2x 1012cm-2. The density of electron trapping centers was found to increase with implant dose, while the associated trapping cross section was much smaller than that of the unimplant oxide.
1. INTRODUCTION
Ion-beam damage of the silicon dioxide has long been an issue of concern in integratedcircuit industry. Arsenic, phosphorus and boron implanted into oxide have been reported to cause significantly higher electron trapping even after high temperature annealingl1-4]. In order to elucidate the nature of implantation induced damage in oxide, we have studied the surface states generation and charge trapping in the polysilicon/Si0 2/Si system as a function of implant dose. The implant ion was chosen to be silicon so that the complication due to substrate doping was eliminated. Fowler-Nordheim tunneling created by constant-voltage stressing was used as the electron injection method. 2. EXPERIMENTAL PROCEDURES
The test devices were N' polysilicon gate MOS capacitors. The structure is schematically shown in Figure 1. The starting material was p-type (100) silicon wafers with resistivity of 30-50 ohm-cm. Si0 2 (43 nm in thickness) was thermally grown in dry oxygen at 950'C, followed by deposition of 0.2 pm of in situ N' doped polysilicon. Prior to oxide growth, the furnace was cleaned with trichloroethylene for 10 hours to minimize contaminations. Silicon ions of 160KeV were then implanted into these samples with ion doses ranging from 5× lxl0 to 1014cm-2. The energy was chosen so that the profile of the implanted silicon ions peaks at the Si/Si0 2 interface. Only half the area of a wafer was implanted. The other half of the wafer was used as a control sample. The wafers were subsequently annealed at 950'C in a nitrogen ambient for 30 minutes. After the polysilicon capacitor patterning, 0.6fim of LPCVD Si0 2 was deposited on the wafers for passivation. The size of the polysilicon gate capacitors ranged from 10-4 to 2.5x 10- 3cm2. The contact holes to the polysilicon capacitors were then patterned and the backsides of the wafers were coated with Al to form an ohmic contact. Finally, the samples were annealed at 450'C in forming gas ( 90% N2 and 10% H2 ) for 30 minutes. To study interface states gen
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