Localized Charge Trapping Memory Cells in a 63 nm Generation with Nanoscale Epitaxial Cobalt Salicide Buried Bitlines
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Localized Charge Trapping Memory Cells in a 63 nm Generation with Nanoscale Epitaxial Cobalt Salicide Buried Bitlines Torsten Mueller1, C. Kleint1, C. Fitz1, M. Isler1, S. Riedel1, J.-U. Sachse1, D. Olligs1, H. Boubekeur1, F. Heinrichsdorf1, V. Polei2, D. Pritchard1, M. Verhoeven1, L. Lattard1, M. Markert1, C. Schupke1, B. Tippelt1, S. Teichert1, R. Reisdorf1, C. Ludwig1, E.G. Stein v. Kamienski1, T. Mikolajick3, and N. Nagel1 1 Qimonda, Koenigsbruecker Strasse 180, Dresden, 01099, Germany 2 Infineon Technologies, Dresden, 01099, Germany 3 Chair of Electronic- and Sensor Materials, University of Mining and Technology, Freiberg, 09596, Germany
ABSTRACT A 63nm Twin Flash memory cell with a size of 0.0225µm2 per 2 (or 4) bits is presented. To achieve small cell areas, a buried bit line and an aggressive gate length of 100 nm are the key features of this cell together with a minimum thermal budget processing. A novel epitaxial CoSi2 process allows the salicidation of local buried bitlines with only a few tens of nanometer width. INTRODUCTION Localized charge trapping memories have been explored as an alternative to today’s floating gate based high-density non-volatile memories due to their attractive bit size [1]. A physically separated storage of two bits within one memory transistor is achieved by localized hot carrier injection into the nitride of an ONO stack (SiO2/Si3N4/SiO2). The mechanism for programming, erase, and reading are channel hot electron injection, band - to - band hot hole tunneling, and a reverse read scheme, respectively [1]. In this paper, we present the device scaling of TwinFlash cells to a 63 nm technology generation (the device width) with a gate length of 100 nm. An aggressive bit size has been possible due to a contact-less planar virtual ground NOR array with local buried bitlines connecting 16 cells [2]. In order to minimize the local buried bitline resistance, we present for the first time an integrative solution for a salicide process to form epitaxial CoSi2 wires with 50nm diameter that allows for further thermal processing up to 1000°C. CELL CONCEPT AND 63 nm TWINFLASH KEY PROCESS FEATURES Localized charge trapping memories require in general a NOR array architecture to allow for hot carrier program and erase. A virtual-ground NOR array is utilized here and in contrast to previous generations with shallow trench isolated cells having local interconnects (LI cells) [3], a planar, contact-less concept with buried local bit lines (BBL cells) is realized (Fig. 1) [2]. The BBL is stitched only every 16 devices by tungsten contacts to the metal bitline, which reduces the unit cell size to 5.76F2 from 6.4F2 in the LI concept. The cell gate length and width is 100 nm and 63 nm with a pitch of 160 nm and 125 nm, respectively. Cross sections in wordline and bitline direction are shown in Fig. 1 (b) and (c). Fig. 2 summarizes the cell sizes, the key process features and the cell operation conditions.
W bit a and b SiO2
buried bit line (a)
poly-Si gate
W poly -Si
ONO layer
(b)
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