Improvement of Threshold Voltage Degradation Characteristics of a-Si:H TFT by Pre-Electrical Bias-Aging for Amoled Displ
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0910-A22-01
IMPROVEMENT OF THRESHOLD VOLTAGE DEGRADATION CHARACTERISTICS OF a-Si:H TFT BY PRE-ELECTRICAL BIAS-AGING FOR AMOLED DISPLAY Jae-Hoon Lee1, Sang-Geun Park1, Kwang-Sub Shin1, Min-Koo Han1, Joon-Chul Goh2, Jong-Moo Huh2, Joonhoo Choi2, and Kyuha Chung2 1 School of Electrical Engineering, Seoul National Univ., #050, San 56-1, Shillim-dong, KwanakKu, Seoul, 151-742, Korea, Republic of 2 SAMSUNG ELECTRONICS CO.,LTD, San #24 Nongseo-Dong, Giheungp-Gu, Yongin-City, Gyeonggi-Do, 449-711, Korea, Republic of
ABSTRACT We propose pre-electrical bias aging to reduce threshold voltage (Vth) shift of hydrogenated- amorphous silicon thin-film transistor (a-Si:H TFT) for AMOLED display. The quantity of Vth shift in the sample subjected to a bias-aging is reduced due to the reduction of created dangling bond density, compared with a sample without a bias-aging. When an identical stress duration of 50,000 sec is applied to a-Si:H TFT with or without a pre-electrical bias-aging, the created dangling bond density (∆ NDB) after a pre-electrical bias-aging is decreased from 1.38 × 1011/cm2 to 0.685 × 1011/cm2. Our experimental results indicate that after the pre-electrical bias aging, the newly created dangling bond during an electrical stress is decreased because the weak bond density and hydrogen diffusion may be decreased.
INTRODUCTION Active matrix organic light emitting diodes (AMOLEDs) have attracted considerable attention due to high brightness, compactness and wide viewing angle [1]. Recently, a-Si:H TFT backplane has been considered as AMOLED backplane because the uniformity and fabrication process for large sized and low cost panel is well established [2]. However, it is well known that the stability of a-Si:H TFT is rather poor, because of Vth shift due to electrical stress. In a-Si:H TFT, the mechanism of Vth degradation due to gate and drain bias are classified into two categories, (1) defect state creation in the a-Si layer and (2) charge trapping into the gate nitride. In the AMOLED display application, low gate-voltages ( < 15V) are required so that the Vth shift of a-Si:H TFT may be mainly due to the creation of dangling bond defects [3-4]. The purpose of our work is to reduce Vth shift of a-Si:H TFT by pre-electrical bias- aging for AMOLED display. The reason why pre-electrical bias-aging reduces Vth degradation of a-Si:H TFT has been analyzed by a photo-induced hole current measurement. Our experimental results show that the reduced Vth degradation after a bias-aging stems from a reduction of newly created defects in the a-Si channel.
EXPERIMENT The a-Si:H TFT used in this experiment, which was an inverted staggered bottom gate type, is fabricated by a standard 5-mask process, as shown in Fig. 1.
(a) Source/Drain metal Passivation
(b) a-Si:H layer n+ layer
Gate Glass substrate
ITO
Gate insulator
Figure 1. Fabricated a-Si:H TFT sample. (a) cross-section view, (b) top-view.
A 250 nm-thick gate metal (Al/Cr) was deposited by sputtering. After gate-metal patterning (#1 mask), 400 nm-thick of silicon ni
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