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U11.13.1

In-situ TEM Studies of Nanoscale Cu Interconnects Under Thermal Stress Jin Ho An and P.J. Ferreira Materials Science and Engineering Program, University of Texas at Austin Austin, TX 78712, U.S.A. ABSTRACT Thermal fatigue during processing of microelectronic devices is a general reliability issue of concern in the microelectronic industry. In particular, as devices continue to be downscaled, the relaxation mechanisms operating under thermal stresses are expected to change. In this study, the microstructure of 1.8 micron and 180 nm wide Cu interconnects was identified through Transmission Electron Microscopy (TEM) imaging. In addition, Insitu TEM heating, performed in both type of specimens, is used to observe the differences in dislocation dynamics under thermal stress. In-situ TEM observations show delamination and inhibited dislocation motion in 180nm Cu lines, whereas in 1.8 micron Cu lines, grain boundaries seemed to act as dislocation sources. These different deformation mechanisms are expected to have an impact on the thermal fatigue behavior of Cu interconnects as the scale of devices is brought below 100 nm. INTRODUCTION During microelectronic device processing, thin films are normally subjected to thermal cycles, from room temperature to approximately 500℃, for the deposition of various materials. These differences in temperature cause metal lines to contract more than the surrounding layers due to a difference in the coefficient of thermal expansion (CTE) among the various layers. As a result, thermal stresses are generated in the metal lines, which can be expressed as [1];

σ thermal =

− E∆α (T2 − T1 ) 1 −ν

(1)

where α is the CTE, E is the elastic modulus, ν is Poisson’s ratio of the film, and T2-T1 is the temperature change. While many studies have been conducted on Cu thin films [2]-[5], Cu interconnects currently used in microchips have a very different environment than thin films. For the particular case of Cu interconnects, thermal stresses are generated due to differences in the CTE between the Cu and 1) the interlayer dielectric (ILD), 2) diffusion barrier (DB), and 3) passivation layer (PL). However, as the demand to downsize device scales persists (current 130 nm nodes operating in most modern computers are scheduled to be reduced to 65 nm nodes by the year 2007 [6]) a crucial question arises: How do thermal stresses change and what are the operating mechanisms, as the structural scale of Cu interconnects is reduced from the micro to nanometer range and the microstructural features of Cu approach the dimensions of the defects? The objective of this paper is thus to identify the differences in grain/defect structure, as well as the stress relaxation mechanisms in micro and nanoscale Cu interconnects through the use of the in-situ transmission electron microscopy. This technique enables us to establish, in real time, a direct relationship between properties and the micro/nano structure of Cu interconnects under different heating and cooling regimes [7]-[11].

U11.13.2

EXPERIMENTAL DE