In-situ TEM Study of Thermally Induced Voids in 180 nm Cu Interconnects
- PDF / 2,184,618 Bytes
- 6 Pages / 595 x 842 pts (A4) Page_size
- 68 Downloads / 159 Views
0907-MM03-03.1
In-situ TEM Study of Thermally Induced Voids in 180 nm Cu Interconnects J.H. An and P.J. Ferreira Materials Science and Engineering Program, University of Texas at Austin Austin, TX 78712, U.S.A. ABSTRACT Cu interconnects have decreased in width and are at around 100 nm. A decrease in interconnect width have led to a predominately bamboo structured Cu lines. In Cu interconnects, void formation during high temperature is a reliability issue, and this study looks at the void formation behavior in damascene Cu interconnects with a predominately bamboo microstructure. First, the crystal texture and grain morphology of the Cu interconnects was observed. Then to determine the void formation behavior, in-situ Transmission Electron Microscopy (TEM) was performed. Voids that formed as a result of in-situ heating were analyzed in terms of preferential void formation sites and crystal orientation where voids formed. In bamboo structured lines, voids formed at the triple junction of grain boundary and Cu/diffusion barrier interface. The crystal orientation where voids nucleated was studied to identify diffusion paths during void nucleation and growth. INTRODUCTION Stress induced void formation in Cu interconnects is a growing concern in the semiconductor industry as interconnects are continuously being downscaled due to the demand for increasing chip speed. Current interconnects have line-widths around 120-180 nm, and are expected to go down to 65 nm by 2007 [1]. The issues of stress induced void formation in Cu interconnects are of particular concern due to an increase in stress levels as the line-width is decreased further [2]. In addition, it has been seen that a decrease in Cu interconnect line-width leads to a different stress relaxation mechanism, i.e. from plastic deformation to void formation [3]. This can be attributed to a change in the stress states from biaxial to quasi-hydrostatic as the interconnect line-widths decrease [4]. Higher stresses leads to higher driving force for stress relaxation, and thus Cu interconnects can be more vulnerable to failure from induced voids. Some attempts to relate texture with void formation has been made in past publications [5,6]. Theses papers suggested the importance of texture in void formation, specifically the role of low and high angle grain boundaries, and the preferential formation of voids in triple points and grain boundary/line edge intersections. However, the research was conducted in considerably wider lines (~1 microns) than those used in current manufacturing processes, and thus not representative of current interconnect grain structures (wider lines can have equiaxed grains within the liens, while thinner Cu lines have typically a bamboo structure). In this context, the objective of this paper is to understand the mechanisms of void formation in electroplated 180 nm Cu interconnects under thermal cycling conditions by using in-situ transmission electron microscopy (TEM). In particular, this work identifies the sites for void formation and grain orien
Data Loading...
