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137 Mat. Res. Soc. Symp. Proc. Vol. 565 0 1999 Materials Research Society

layers). Using the second low-K integration scheme can alleviate many processing issues related to low-Kc materials and improve the mechanical strength and heat dissipation of the interconnect structures [6,7]. However, the interconnect capacitance improvement in the second scheme is limited in comparison to the first scheme. Fig. I and Fig. 2 show calculated interconnect wiring capacitance as a function of metal linewidth/space for low-K (K = 2) interconnects of the first scheme (homogeneous low-K) and the second scheme (embedded low-K) and they are compared to the interconnects with SiO 2 (K = 4) ILD. Fig. 1 shows a scaling scenario where the vertical dimensions (metal height and space between the metal layers) are kept constant and only horizontal dimensions (metal linewidth and space) are scaled. The shaded area in Fig. 2 corresponds to a scaling scenario where the vertical dimensions of the interconnect structures are scaled by the same factor as the horizontal dimensions. In this case, the metal line aspect ratio (AR) is a constant as the interconnect linewidth/space is reduced.

on

-*-I I

iI 0.60-

U.

0.40 0.30

cc

S•i02 ( k=4 )

-,- Si02 (k=4 ) --- embedded low-k -- homogeneous low-k lw-k: =2

E 0.50

m-4II

+Fixed Aspect Ratio

Fixed Vertical Dimension E

embedded low-k homogeneous low-k

a)L 0,

low-k: k=2

C

a) a-

0.20

0.

0.

0.10 0.001 -

0.00

0.20

0.40

0.60

0.80

0.00

1.00

Linewidth/Space ( pm )

0.20

0.40

0.60

0.80

1.00

Linewidth/Space ( itm)

Fig. 1 Wiring capacitance for interconnects of different ILD for the scaling of constant interconnect vertical dimensions (metal height and space between metal layers).

Fig. 2 Wiring capacitance for interconnects of different ILD and the shade area correspond to the scaling of constant aspect ratio for the interconnect features.

For the scaling of fixed interconnect vertical dimensions, as shown in Fig. 1, the interconnect wiring capacitance increases very rapidly as the metal linewidth/space is scaled down to less than 0.25ptm for the interconnect of SiO 2 ILD. Homogeneous low-K ILD or embedded low-K ILD can significantly reduce the interconnect capacitance. In comparison, the interconnect capacitance is kept at a constant in the case where both horizontal and vertical scaling have occurred as shown in Fig. 2. For this scaling scenario, appreciably more capacitance reduction can be obtained in the interconnect of homogeneous low-K ILD in comparison to the interconnect of embedded

138

low-K ILD. Since the cross-sectional area of the conductor lines is reduced more severely in the scaling of fixed interconnect AR, it leads to dramatic increase in interconnect wiring resistance. In addition, the dramatically increased current density could lead to interconnect electromigration problems. To overcome these issues, new conductive materials of better conductivity and larger electromigration resistance are required for the interconnect lines. There are many tradeoff cons