Interface and Electrical Properties of Atomic-layer-deposited HfAlO Gate Dielectric for N-channel GaAs MOSFETs
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Interface and Electrical Properties of Atomic-layer-deposited HfAlO Gate Dielectric for Nchannel GaAs MOSFETs Rahul Suri1, Daniel J. Lichtenwalner2 and Veena Misra1 1 Electrical and Computer Engineering, North Carolina State University, Raleigh, NC, 27695 2 Materials Science and Engineering, North Carolina State University, Raleigh, NC, 27695 ABSTRACT The interface and electrical properties of HfAlO dielectric formed by atomic layer deposition (ALD) on sulfur-passivated GaAs were investigated. X-ray photoelectron spectroscopy (XPS) revealed the absence of arsenic oxides at the HfAlO/GaAs interface after dielectric growth and post-deposition annealing at 500 °C. A minimal increase in the amount of gallium oxides at the interface was detected between the as-deposited and annealed conditions highlighting the effectiveness of HfAlO in suppressing gallium oxide formation. An equivalent oxide thickness (EOT) of ~ 2 nm has been achieved with a gate leakage current density of less than 10-4 A/cm2. These results testify a good dielectric interface with minimal interfacial oxides and open up potential for further investigation of HfAlO/GaAs gate stack properties to determine its viability for n-channel MOSFETs. INTRODUCTION Recently, III-V semiconductor materials such as GaAs, because of their high electron mobility, have gained significant attention as alternative channel materials for scaling of nchannel metal-oxide-semiconductor field effect transistors (MOSFETs). In order to achieve high performance (high speed and low power) GaAs MOSFETs at 22 nm technology node and beyond, a high quality interface between the high-k gate dielectric and GaAs substrate is imperative. Significant research efforts have focused on surface passivation of GaAs as well as finding a high quality and thermodynamically stable high-k dielectric on GaAs. HfO2, by itself, on GaAs yields poor electrical characteristics because of native oxide growth during dielectric deposition and annealing [1]. The formation of native oxides (Ga and As oxides) renders the interface with a large interface state density which causes Fermi level pinning and hampers the device electrical performance. The approach of using an interface passivation (IPL) layer prior to HfO2 deposition has yielded convincing results. Relatively low EOT and low gate leakage have been achieved by employing an IPL such Si [2,3], Ge [4] and GexNy [5]. However, in order to achieve the lowest possible EOT gate stacks, and avoid issues related to having a lower mobility semiconductor IPL, it is of practical importance to investigate and establish a high-k dielectric on GaAs that yields a good quality interface without requiring an additional IPL. This necessitates the need of a surface passivation technique that effectively removes the native oxides prior to dielectric deposition and a high-k dielectric that retards its formation during dielectric growth and post-annealing. Suppression of native oxide growth at the interface is one key requirement towards obtaining high performance d
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