Hetro-Dielectric (HD) Oxide-Engineered Junctionless Double Gate all around (DGAA) Nanotube Field Effect Transistor (FET)
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ORIGINAL PAPER
Hetro-Dielectric (HD) Oxide-Engineered Junctionless Double Gate all around (DGAA) Nanotube Field Effect Transistor (FET) Raj Kumar 1
&
Arvind Kumar 1
Received: 18 August 2020 / Accepted: 8 September 2020 # Springer Nature B.V. 2020
Abstract This paper proposed Hetero-Dielectric (HD) Oxide-Engineered Junctionless double gate all around nanotube (DGAA-NT) FET for performance enhancement in low power circuits. In HD configuration, hafnium based high-k dielectric (HfO2 and HfxTi1xO2) as gate oxide (for inner as well as outer gate oxide) is introduced on source side and SiO2 on drain side of HD JL-DGAA-NT FET. The tunnelling width and source-to-channel barrier height are significantly increased in the HD-JL-DGAA-NT FET as compared JL-DGAA-NT FET, causes the reduction in leakage current an order of 10−14 to 10−17 and ION/IOFF ratio increased by 54%. It has been observed that side spacer with suitable dielectric constant can be considered to improve the performance of device. Further, Subthreshold slope (SS) and DIBL and ION/IOFF current ratio has shown tremendous improvement on reducing channel thickness from 10 nm to 8 nm. It has been found that in HD-JL-DGAA-NT FET provides 25% and 57% improvement in SS and DIBL respectively. Therefore, HD-JL-DGAA-NT FET with adequate design parameters and dielectric material may be used for future digital applications. Keywords Hetro-dielectric (HD) . Nanotube (NT) . Junctionless . DIBL . SS . Leakage current
1 Introduction As the feature size of device migrating below 20 nm, many unavoidable detrimental effects such drain induced barrier lowering (DIBL), threshold voltage roll-off, sub-threshold swing (SS), velocity saturation and large drain-off current have confined the performance of device [1–4]. Fabrication process of highly sharp p-n junctions at source/drain with channel in inversion-mode transistor has become a huge challenge owing to the laws of diffusion and the statistical nature of the distribution of the doping atoms in the semiconductor [5, 6]. To deal with aforementioned fabrication issues, junctionless transistors (JLT) were proposed, fabricated and investigated [5–9]. JLT has shown a lower susceptibility to the short channel effects (SCEs). However, JLTs provides lower ON-current as compared to conventional MOSFETs attributed to low source/drain doping. Furthermore, various multigate
* Raj Kumar [email protected] 1
University Institute of Engineering and Technology, Panjab University, Chandigarh, India
junctionless MOSFETS such as double gate JL MOSFET, and junctionless gate all around nanowire MOSFET (JL-GAA-NW MOSFET) have been designed to enhance the performance of JLFETs [10, 11]. The gate-all-around (GAA) nanowire (NW) structure is possess efficient gate control, leading to a significant proximity between the valence band of channel region and conduction band of drain region in the OFF-state [12–15].Thereby, the lateral band-to-band-tunnelling (L-BTBT) of electrons from the channel to the drain is responsible to create a parasitic
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