Kinetics of Void Drift in Copper Interconnects

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Kinetics of Void Drift in Copper Interconnects Zung-Sun Choi1, Reiner Mönig1, Carl Vernette Thompson1, and Michael Burns2 1 Materials Science and Engineering, Massachusetts Institute of Tecnology, 77 Massachusetts Avenue, Cambridge, MA, 02139 2 Rowland Institute at Harvard, 100 Edwin H. Land Boulevard, Cambridge, MA, 02142 ABSTRACT We have observed the real-time behavior of electomigration-induced voids in both passivated and unpassivated copper interconnects in a Scanning Electron Microscope (SEM), and correlated void nucleation, growth, drift and stagnation with post-electromigration crystallographic microanalyses carried out using Electron Back-Scattered Diffraction (EBSD) analysis. Voids that nucleate at various locations along the interconnects often drift toward the cathode, where they grow, coalesce, and eventually cause electrical failure. In-situ SEM observations allowed for the tracking of void shapes and drift rates over long (multi-grain) distances. Changes in the size and the velocity of the voids were observed when the voids passed through different grains. These changes are attributed to the difference in diffusivity for different grain orientations. In passivated lines, voids were often trapped at individual grain boundaries, where they grew to cause failure, or de-trapped to continue to drift toward the cathode. In unpassivated lines, voids did not drift, but instead always nucleated and grew and grain boundaries. Locations at which voids grew in unpassivated lines, or at which voids were trapped and grew in passivated lines, were correlated with the crystallographic orientations of “upwind” and “downwind” grains. From these analyses, we find that the average electromigration interface diffusivities (z*D) as a function of grain orientation are ordered according to {100} > {111} > {110}. Quantitative analysis of void dynamics, correlated with crystallographic microanalyses, provides important data for modeling of electromigrationinduced failure, and for process-optimization for improved reliability. INTRODUCTION High performance integrated circuits require high current densities in low-resistance copper on-chip interconnects [1]. This, in turn, requires continuous improvement of the reliability of Cu-based interconnects. Cu reliability is limited by electromigration-induced voiding. Electromigration occurs along fast-diffusion paths such as grain boundaries or interfaces [2]. For copper interconnects, the relevant interfaces are those with the metallic diffusion-barrier liner on the two sides and the bottom of the line, and the interface with a dielectric overlayer (often Si3N4). The dielectric overlayer not only serves as an etch-stop and barrier to the out diffusion of Cu, it also serves as a bonded ‘passivation’ layer that ideally serves to suppress void formation and to reduce interface electromigration rates. However, electromigration studies have shown that the Cu-overlayer interface usually provides the dominant high diffusivity path for electromigration [3-6] and is the site at w