Quantum Dot Gate Field-Effect Transistor (QDGFET): Circuit Model and Ternary Logic Inverter
The circuit model of QDGFETs is introduced in Chapter 6. This chapter highlights the modification of BSIM MOSFET model based on the characteristic of the QDGFET. Standard ternary logic inverter (STI) is also discussed in this chapter. The circuit simulati
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Quantum Dot Gate Field-Effect Transistor (QDGFET): Circuit Model and Ternary Logic Inverter
The circuit model of QDGFETs is introduced in this chapter. This chapter highlights the modification of BSIM MOSFET model based on the characteristic of the QDGFET. Standard ternary logic inverter (STI) is also discussed in this chapter. The circuit simulation of NMOS inverter and the comparison between experimental data and simulation results is also presented in this chapter. The drawback of QDGFET-based STI is also discussed in this chapter which is followed by the three-state memory cell based on QDGFET. BSIM [1, 2] is a physics-based, accurate, scalable, robustic, and predictive MOSFET SPICE model for circuit simulation and CMOS technology development. It is developed by the BSIM Research Group in the Department of Electrical Engineering and Computer Sciences (EECS) at the University of California, Berkeley. The third iteration of BSIM3, BSIM3 Version 3 (commonly abbreviated as BSIM3v3), was established by SEMATECH as the first industry-wide standard of its kind in December of 1996. BSIM3v3 has since been widely used by most semiconductor and IC design companies worldwide for device modeling and CMOS IC design. This chapter provides the modification of BSIM model to simulate the QDGFET electrical characteristics.
6.1
QDGFET Circuit Model
An empirical circuit model [3, 4] is developed for the QDGFET that accounts for the intermediate state “i” which manifests within the range of gate voltages Vg1 and Vg2. The effective threshold voltage is divided into three ranges corresponding to the three regions of the transfer characteristics (see Fig. 6.3): region 1, intermediate state “i,” and the saturation region.
S. Karmakar, Novel Three-state Quantum Dot Gate Field Effect Transistor: Fabrication, Modeling and Applications, DOI 10.1007/978-81-322-1635-3_6, © Springer India 2014
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6 Quantum Dot Gate Field-Effect Transistor (QDGFET). . .
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V Teff
8 < VT ¼ V T þ αV GS V g1 : V T þ α V g2 V g1
V GS < V g1 V g1 < V GS < V g2 V GS > V g2
(6.1)
As the gate voltage increases through a range of voltages (Vg1 to Vg2), the threshold voltage changes linearly with respect to the gate voltage. The effect is controlled by the α parameter. With α ¼ 0, the QDGFET behaves like a conventional FET, and with α ¼ 1, the QDGFET has a threshold voltage that changes directly with the gate voltage. This α parameter can be controlled by the thickness of various insulators, and by changing the size and number of dots, that results in changing of the QD gate charge. Likewise, the Vg1 and Vg2 values are also determined by the device structure. Using the equations for VTeff from Eq. 6.2, we can give the drain current equations using traditional MOSFET circuit modeling techniques.
I DS
8 0 > 0 1 > > > > W V > DS > AV DS < Co μ@V GS V Teff L 2 ¼ > 2 > > > V GS V Teff W > > > : L Co μ 2
V GS < V Teff V DS < V GS V Teff (6.2) V DS > V GS V Teff
When α ¼ 1, VTeff ¼ VT + VGS Vg1, meaning that IDS I DS ¼ WL Co μ V
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