Modeling of Dislocations in an Epitaxial Island Structure
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Modeling of Dislocations in an Epitaxial Island Structure X. H. Liu, F. M. Ross and K. W. Schwarz IBM Watson Research Center, P.O. Box 218 Yorktown Heights, NY 10598, U.S.A.
ABSTRACT We present calculations of dislocations in CoSi2 islands grown by reactive epitaxy on a Si(111) substrate. The stress elds due to the lattice mismatch are calculated with standard FEM techniques, and are converted into a structured, multi-level and multi-grid stress table that is imported into the PARANOID code to study the dislocation dynamics. Single and multiple dislocations in the island have been simulated, and the predicted patterns are strikingly similar to those observed experimentally. By looking at the growth behavior of very small loops we also nd that dislocation-loop nucleation becomes easier as the islands become larger, and that thick islands are dislocated at smaller sizes than thin ones. These results are also in good agreement with experimental observations. We conclude that current modeling techniques are suÆcient to treat this type of problem at a useful level of accuracy.
INTRODUCTION Dislocations are linear defects in crystals which mark the places where atomic planes have slipped relative to each other. The nucleation and motion of these defects in uence such mechanical properties as strength, hardness, and fracture toughness. Because of this, dislocations have historically been studied with an emphasis on the mechanical properties of bulk materials. More recently, however, dislocations have become a topic of interest in the manufacture of semiconductor lms and devices, where they provide electrical leakage paths which can ruin device performance. In such a situation, the task is to understand the behavior of just a few dislocations in a highly con ned geometry. As a paradigm of such a problem, we examine the growth of dislocations in certain island structures which form spontaneously during epitaxial growth. Such dislocated islands provide an ideal environment in which to study dislocations in small structures. A preliminary report on this work has been published elsewhere [1]. In the semiconductor industry, device structures are fabricated through the repeated application of a number of basic processing steps involving epitaxy, photolithography, deposition, etching, oxidation, di usion, ion implantation, evaporation or sputtering, and chemicalmechanical polishing. Many of these processes generate large stresses, which may initiate and drive dislocations into the device. In contrast to bulk materials, the stresses in devices are often caused, not by mechanical loads, but by mismatches in physical properties such as thermal expansion and the varying lattice constants of the various materials used in device fabrication. Although the dislocation density is comparable for bulk materials and semiconductor structures, the number of dislocations in devices is signi cantly fewer because of their small size. This renders continuum plasticity theory, developed to study the plastic behaviors of bulk materials with million
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