More physical understanding of current characteristics of tunneling field-effect transistor leveraged by gate positions
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More physical understanding of current characteristics of tunneling field‑effect transistor leveraged by gate positions and properties through dual‑gate and gate‑all‑around structuring Md. Hasan Raza Ansari1 · Seongjae Cho1 · Byung‑Gook Park2 Received: 30 May 2020 / Accepted: 22 September 2020 © Springer-Verlag GmbH Germany, part of Springer Nature 2020
Abstract In this work, a tunneling field-effect transistor (TFET) in the structure that can maximize the electrostatic effects in determining its electrical performances is optimally designed and characterized. The featured device structure includes gate-all-around (GAA) channel and dual gates (DuGs) identified as control gate (CG) and adjust gate (AG), respectively. Not along with the design tasks, more fundamental studies on the effects of respective gates on device performances are sought. It has been found that the relatively different vicinities of the DuGs to source and drain junctions have differentiable dominances in controlling the primary direct-current (DC) parameters of the TFET including threshold voltage (V th), on-state current (Ion), subthreshold swing (S), and on/off current ratio (Ion/Ioff). For the systematic study, four different cases have been presumably schemed giving the degree of freedom in gate workfunctions and inter-gate connectivity. It has been found that the CG at the source side more effectively modulates Vth, Ioff, and S, while the AG at the drain side shows the higher controllability over Ion and Ion/Ioff of the TFET. An optimally designed GAA DuG demonstrated Ion/Ioff > 1011 along with a small S of 14.6 mV/dec, which supports the strong potential of the GAA DuG TFET in the low-power applications. Keywords Tunneling field-effect transistor · Dual-gate structure · Gate-all-around channel · Low-power operation · Gate controllability · Nanoscale transistor design
1 Introduction Increases in the demand on tremendously massive data and corresponding hardware technologies require new device design and miniaturization of semiconductor devices [1–3]. Downscaling in the conventional metal–oxide–semiconductor field-effect transistor (MOSFET) leads to various types of short-channel effects (SCEs) which substantially degrade the device and system performances [4–6]. Representatively, to enhance the gate controllability significantly threatened by the SCEs, a multiple-gate (MuG) structure has been widely used [4], along with the various carrier
* Byung‑Gook Park [email protected] 1
Department of Electronic Engineering, Gachon University, Seongnam, Gyeonggi‑do 13120, Republic of Korea
Inter‑University Semiconductor Research Center (ISRC) and Department of Electrical and Computer Engineering, Seoul National University, Seoul 08826, Republic of Korea
2
transport mechanisms [2, 7]. A promising candidate for the MOSFET structure in the near future would be the gate-allaround (GAA) structure, and furthermore, it is very probable for tunneling field-effect transistor (TFET) to appear in the technology roadmap in the near future [2, 6, 8–
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