N+/P and P+/N Junctions in Strained Si on Strain Relaxed SiGe Buffers: the Effect of Defect Density and Layer Structure
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N+/P and P+/N Junctions in Strained Si on Strain Relaxed SiGe Buffers: the Effect of Defect Density and Layer Structure G. Eneman1,2,3, E. Simoen1, R. Delhougne1, P. Verheyen1, M. Ries4, R. Loo1, M. Caymax1, W. Vandervorst1,2, K. De Meyer1,2 1 IMEC vzw, Kapeldreef 75, 3001 Leuven, Belgium 2 K.U. Leuven, ESAT-INSYS, 3001 Leuven, Belgium 3 Research assistant of The Fund for Scientific Research – Flanders (Belgium) 4 MEMC Electronic Materials, PO Box 8, 501 Pearl Drive, Saint Peters, MO, 63376, USA ABSTRACT The electrical performance of junctions in SiGe Strain Relaxed Buffers (SRB’s) with a strained Si top layer is investigated. Most of the SRB’s grown in this experiment use a thin Cdoped SiGe layer, which allows to fabricate thin (~250nm) SRB’s with a high relaxation degree. The effects of Threading Dislocation Density (TDD) and C-rich layer depth on the electrical behaviour of n+/p and p+/n junctions are studied. The C atoms in the junction’s Space Charge Region (SCR) give rise to defects and induce a noticeable increase in the leakage. The effect of the TDD on the leakage in n+/p junctions is linear over the complete voltage range applied, while for p+/n junctions, only a small effect on leakage is measured at V=1V reverse for TDD’s below 1x107cm-2. For low reverse voltages, the current varies more linearly with TDD. INTRODUCTION Silicon-germanium SRB’s with a strained Silicon top layer are widely regarded as a manufacturable way to enhance the mobility in MOSFET transistors [1-2]. Until now, these SRB’s have been most successful in improving the nMOS performance, while enhancing pMOS performance seems to be less evident. It is an important challenge in SRB’s to keep the junction leakage under control. The leakage in SiGe is expected to be higher than in silicon because of a decreased bandgap. Growing a relaxed SiGe layer on a silicon substrate also needs a controlled relaxation of the virtual substrate. In the ideal case, the dislocations are formed well below the silicon surface, leaving the top-200nm of the virtual buffer defect-free. However, it is difficult to avoid threading dislocations that run from the SiGe/substrate interface to the strained Si top layer. These threadings will have an influence on the junction leakage, and may cause yield problems in CMOS processes. Junctions have been fabricated in SRB layers that use a C-doped layer to induce a high relaxation of the SiGe virtual substrate. The depth of this C-rich layer was varied with respect to the junction, as well as the number of threadings in the layers. It is the goal of this paper to study the effect of Threading Dislocation Density (TDD) and the position of the C-rich layer on the leakage measured in large-area diodes. EXPERIMENTAL SETUP Large-area diodes (Area=1x105µm2) were fabricated by standard HDD and well implantations, placing the metallurgical junction at a depth of ~80nm below the surface. An implant mask was used to pattern the junctions (Figure 1). All wafers received a standard
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Figure 1. Overview of the layers, us
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