Analysis of junctions formed in strained Si/SiGe substrates
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Analysis of junctions formed in strained Si/SiGe substrates G. Eneman1,2,4, E. Simoen1, A. Lauwers1, R. Lindsay1, P. Verheyen1, R. Delhougne1,2, R. Loo1, M. Caymax1, P. Meunier-Beillard3, S. Demuynck1, K. De Meyer1,2, W. Vandervorst1,2 1 IMEC vzw, Kapeldreef 75, B-3001 Leuven, Belgium 2 K.U.Leuven, ESAT-INSYS, 3001 Leuven, Belgium 3 Philips Research Leuven, affiliated to the IMEC/LD Group 4 Research assistant of The Fund for Scientific Research – Flanders (Belgium) ABSTRACT Junctions were formed in thin SiGe/strained Si substrates with a thickness of 250-350 nm to assess the effect of different buffer layer parameters (bandgap, dislocations, thickness) on the junction leakage density that can be expected in MOSFET devices. The implantations used are standard well, channel and Highly Doped Drain (HDD) implants. Both p+/n and n+/p junctions were evaluated. The total thickness of the buffer layers was varied to compare the effect of different structural layers on the diode leakage. This investigation shows that the effect of an increased defect density is dominant at room temperature for the strained Si samples, resulting in 4-5 orders of magnitude increase in leakage. However, there is a different gradation in leakage dependence for thick and thin buffer layers, especially at higher temperatures. INTRODUCTION Strained Si (SSi) on a silicon-germanium (SiGe) virtual substrate is an interesting candidate to overcome the performance issues that are encountered when devices are scaled down to nanometer-scale dimensions. Due to band splitting and effective mass reduction, these strained silicon transistors have a high mobility for electrons and holes [1-4]. The growth of SiGe virtual substrates on a Si wafer requires a well-controlled relaxation of the SiGe layer, to ensure that transistor operation does not suffer from excessive leakage caused by threading dislocations, coming up to the strained Si channel and junctions. Standard SiGe buffer layers try to overcome this problem by using a graded-buffer structure. This structure is fabricated by alternating growth steps and temperature treatments to relax the layers. These layers have a thickness in the order of 1-5 µm. In thick buffer layers, the negative influence of dislocations on diode leakage and device performance is a known problem [3,5]. Thin buffer layers have several advantages over thick layers, such as better thermal conductivity, as well as a reduced cost and the possibility to grow selectively. In this paper, thin buffer layers with a total thickness of 250-350nm are evaluated. The thickness of these layers was varied to study its effect on junction leakage. Temperature measurements allowed us to trace the generation mechanisms of the leakage. EXPERIMENTAL SETUP The SiGe buffer layers are grown in an ASM 2000 epsilon reactor, using a three-step growth process [6-8]. These buffers consist of a Si0.78Ge0.22 layer, containing a C-rich layer of ~5nm, and a Si0.8Ge0.2 layer with a variable thickness, with 8nm strained Si on top (Figure 1, left). The Crich l
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