Porous Alumina Template based Versatile and Controllable Direct Synthesis of Silicon nanowires
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Porous Alumina Template based Versatile and Controllable Direct Synthesis of Silicon nanowires Ki-Hwan Kim, Emmanuel Lefeveure, Marc Châtelet, and Costel-Sorin Cojocaru LPICM, UMR 7647, Ecole Polytechnique Route de Saclay, 91128 PALAISEAU, FRANCE ABSTRACT Highly densely packed, self-organized silicon nanowires with very narrow diameter distribution were synthesized within porous anodic alumina templates with electrodeposited catalytic metal nanoparticles. For successful catalytic metal nanoparticle deposition, electrochemical-, and chemical barrier layer thinning process was investigated following anodization process. Controlled pulsed electrodeposition process was carried out for a volume calibration of desired catalytic metal nanoparticle deposition inside nanopore arrays using different metal-ion containing electrolyte. Not only single metal nanoparticles, but also multi metal nanoparticles layers were filled inside PAA to enhance metal filling aspect, and to control the volume of nanoparticles more precisely. Using multilayered metal nanoparticles resulted on different SiNW’s growth behavior depending on the types of underlying metal nanoparticles. SiNWs were successfully synthesized using hot-filament assisted chemical vapor deposition system. Although silicon precursor gas can generally be dissociated at relatively low temperatures, the use of a hot filament activation help decreasing process temperature, and also, highly activated atomic hydrogen generation via the tungsten hot filament placed at gas inlet helps preventing parasitic amorphous silicon deposition on either the alumina membrane surface or the pore wall which hinders appropriate growth of SiNWs in PAA by nanopores clogging. Such densely packed, self-organized SiNWs are of high interest in many application fields like nanoelectronics, optoelectronics, and energy storage/conversion devices etc. INTRODUCTION Quasi one-dimensional (1-D) semiconducting nanowires such as silicon(Si), germanium(Ge), gallium arsenide(GaAs), indium phosphide (InP), cadmium selenide(CdSe) nanowires are of high interest as alternative materials for future electronics[1]. Especially silicon nanowires(SiNWs) have been considered one of the most promising materials as building blocks for future nanoelectronics, optoelectronics, and energy storage/conversion devices due to their excellent physical, electrical, and optical properties. SiNWs have already demonstrated high potential for application in field-effect transistors(FETs) [2], solar cells[3], chemical and biosensors[4], Li-ion battery electrode[5] and so on. Nowadays SiNW-based devices are fabricated following both top-down[6] and bottom-up[6] approaches. The top-down approach combines high quality of SiNWs and uniform array fabrication, but the process is time consuming, and poor substrate flexibility is available . On the contrary, the bottom-up approach, especially chemical vapor deposition(CVD) based process, has recently shown high potential to synthesize semiconductor nanowires for future applications[6]. For such
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