Process-Induced Strained P-MOSFET Featuring Nickel-Platinum Silicided Source/Drain
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0913-D02-04
Process-Induced Strained P-MOSFET Featuring Nickel-Platinum Silicided Source/Drain Rinus Tek Po Lee1, Tsung-Yang Liow1, Kian-Ming Tan1, Kah-Wee Ang1, King-Jien Chui1, Qiang-Lo Guo2, Ganesh Samudra1, Dong-Zhi Chi3, and Yee-Chia Yeo1 1 Electrical and Computer Engineering, National University of Singapore, Silicon Nano Device Laboratory, Singapore, Singapore, 119260, Singapore 2 Institute of Microelectronics, 11 Science Park Road, Science Park-II, Singapore, Singapore, 117685, Singapore 3 Institute of Materials Research and Engineering, 3 Research Link, Singapore, Singapore, 117602, Singapore ABSTRACT We report the use of nickel-platinum silicide (NiPtSi) as a source/drain (S/D) material for strain engineering in P-MOSFETs to improve drive current performance. The material and electrical characteristics of NiPtSi with various Pt concentrations was investigated and compared with those of NiSi. Ni0.95Pt0.05Si was selected for device integration. A 0.18 µm gate length PMOSFET achieved a 22% gain in IDsat when Ni0.95Pt0.05Si S/D is employed instead of NiSi S/D. The enhancement is attributed to strain modification effects related to the nickel-platinum silicidation process. INTRODUCTION Strained silicon technology has recently been actively explored for the improvement of drive current IDsat and carrier mobility in metal-oxide-semiconductor field-effect transistors (MOSFETs) [1-5]. One of the most cost-effective and manufacturable options of introducing strain in the transistor channel is through the exploitation of process-induced strain. Processinduced strain can be introduced at various process steps during transistor fabrication, e.g. metal silicidation of source/drain (S/D), shallow-trench isolation, and contact-etch-stop layer [2-4]. With the reduction of the transistor gate length LG, strain induced by the metal silicide in the S/D regions becomes increasingly significant. Engineering the strain due to the silicided S/D could be an attractive approach to further enhance the IDsat performance. Recently, both N- and PMOSFETs have been reported to exhibit improved transconductance Gm and IDsat resulting from silicide-induced strain in the S/D region [2, 5]. Currently, studies on silicide-induced strain focus on cobalt silicide (CoSi2) and nickel silicide (NiSi). The origin of this strain is attributed to the reduction in volume during silicidation, the mismatch of the thermal expansion coefficients of silicide and silicon, or the lattice mismatch between the silicide and silicon. Volume reduction during silicidation and the mismatch in thermal expansion coefficients of silicide and silicon play an important role in the introduction of strain in the transistor channel (Figure 1). Modification of the induced strain through silicide materials engineering could be explored for device performance enhancement. In this paper, we report a novel approach for improving the drive current performance in P-MOSFETs by employing nickel-platinum as the S/D silicide material. The material characteristics of nickel-platinum
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