Sub-30 nm FinFETs with Schottky-Barrier Source/Drain Featuring Complementary Metal Silicides and Fully-Silicided Gate fo
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Sub-30 nm FinFETs with Schottky-Barrier Source/Drain Featuring Complementary Metal Silicides and Fully-Silicided Gate for P-FinFETs Rinus Tek Po Lee1, Kian-Ming Tan1, Tsung-Yang Liow1, Andy Eu-Jin Lim1, Guo-Qiang Lo2, Ganesh S. Samudra1, Dong-Zhi Chi3, and Yee-Chia Yeo1 1 Electrical and Computer Engineering, National University of Singapore, Block E4A #02-04 Engineering Drive 3, Singapore, 117576, Singapore 2 Institute of Microelectronics, 11 Science Park, Singapore, 117685, Singapore 3 Institute of Materials Research and Engineering, 3 Research Link, Singapore, 117602, Singapore ABSTRACT We investigated the material and electrical characteristics of platinum and ytterbium silicides for potential applications as metallic Schottky-barrier source/drain (S/D) and fullysilicided (FUSI) gate electrodes in fin field-effect transistors (FinFETs). Due to the low electronegativity parameter of ytterbium, a low temperature silicidation process was developed to avoid the reaction of ytterbium with the isolation regions (i.e. SiO2 and SiN) to integrate ytterbium silicide successfully in mesa-isolated n-FinFETs. The integration of FUSI metal gate into pFinFETs was also explored in this work and a novel two-step silicidation process that integrates simultaneously two different phases of platinum silicide with the appropriate work function values for gate electrode and source/drain application was demonstrated. INTRODUCTION Dimensional scaling of complementary metal-oxide-semiconductor (CMOS) technology has provided significant improvements in integrated circuit density and device performance. However, continual dimensional scaling into the nanoscale regime has led to immense technological challenges; therefore non-classical transistor structures will have to be seriously considered [e.g. double-gate or triple-gate transistors] to further extend the limits of device performance. In addition, various ëtechnology boostersí such as metal gate electrodes and metallic source/drain regions (e.g. metal silicides) could be implemented in these device structures. These devices [i.e. FinFETs or multiple-gate transistors] offer superior control of short-channel effects and enable scalability well beyond the 22 nm technology node [1]. On the other hand, Schottky-Barrier source/drain (S/D) transistors [2], which replace the highly-doped S/D junction with a metallic junction offer low sheet and specific contact resistance. In addition, Schottky-Barrier S/D (SSD) provides well-controlled junction depth and abruptness, minimize overlap capacitance, and a reduced thermal budget for the integration of metal gates on high-κ dielectrics. Therefore the integration of SSD and FUSI technologies in FinFETs might potentially achieve the ultimate device scalability. In this paper, we investigate the material and electrical characteristics of ytterbium and platinum silicides. Platinum monosilicide (PtSi) [Φp = 0.24 eV] and ytterbium silicide (YbSi1.8) [Φn = 0.27 eV] are the two most ideal silicide materials for SSD applications as they possess
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