A 12-bit 800 MS/s Dual-Residue Pipeline ADC
This paper presents the design of a pipeline analog-to-digital converter (ADC) based on the dual-residue principle. By applying this technique, the ADC becomes insensitive to the exact gain of the MDAC residue amplifiers. This allows these amplifiers to b
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A 12-bit 800 MS/s Dual-Residue Pipeline ADC Jan Mulder, Davide Vecchi, Frank M.L. van der Goes, Jan R. Westra, Emre Ayranci, Christopher M. Ward, Jiansong Wan, and Klaas Bult
Abstract This paper presents the design of a pipeline analog-to-digital converter (ADC) based on the dual-residue principle. By applying this technique, the ADC becomes insensitive to the exact gain of the MDAC residue amplifiers. This allows these amplifiers to be designed with a relatively low open-loop gain and low bandwidth, which is favorable for the power consumption of the ADC. The offsets of the residue amplifiers, however, limit the accuracy of the ADC. Therefore, offset calibration is required for the ADC to achieve a high resolution. A 12-bit 800 MS/s dual-residue ADC was designed and implemented in a standard 40 nm CMOS technology. The high sampling speed was obtained through four times interleaving. The ADC achieves a peak SNDR of 59 dB. It operates from a dual 1 V/2.5 V power supply and consumes 105 mW.
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Introduction
The increasing demands of telecommunication systems are continuously pushing the specifications of integrated circuits. Whereas digital processing can exploit the improvements introduced by deep-submicron technologies, analog interface circuits may be negatively affected by technology scaling. In particular, power supply scaling and intrinsic transistor gain reduction significantly influence the design of high performance analog components.
J. Mulder (*) • D. Vecchi • F.M.L. van der Goes • J.R. Westra • C.M. Ward • J. Wan • K. Bult Broadcom Netherlands B.V., Bunnik, The Netherlands e-mail: [email protected] E. Ayranci Now with ClariPhy Communications Inc., Irvine, CA, USA A.H.M. van Roermund et al. (eds.), Nyquist AD Converters, Sensor Interfaces, and Robustness: Advances in Analog Circuit Design, 2012, DOI 10.1007/978-1-4614-4587-6_2, # Springer Science+Business Media New York 2013
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High resolution (i.e., > 10 bit) and high conversion rate (> 100 MS/s) are typical requirements today for ADCs. To allow integration on a large System-ona-Chip (SoC), there are additional limitations on area and power consumption. Pipeline ADCs, given their area and power efficiency, are an excellent architecture to fulfill these requirements [1–9]. Pipeline ADCs, however, suffer from an important limitation: Their linearity is limited by the finite open-loop gain and finite bandwidth of the residue amplifiers. To improve the gain and bandwidth of these amplifiers, design techniques leading to higher power consumption must be implemented. To reduce this power penalty, several calibration algorithms have been proposed [10–12], that can calibrate either for the gain-induced errors (and the incomplete settling due to limited bandwidth) [12] or for the nonlinearity of the residue amplifiers [10] or both [1]. Foreground calibration algorithms cannot track changes caused by temperature, voltage, and aging. On the other hand, background calibrations require long convergence times, making them unsuitable for
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