A Memory Reliability Enhancement Technique for Multi Bit Upsets
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A Memory Reliability Enhancement Technique for Multi Bit Upsets Alexandre Chabot1,2
´ Nouacer2 · Smail Niar1 · Ihsen Alouani3 · Reda
Received: 14 October 2019 / Revised: 2 July 2020 / Accepted: 5 October 2020 © Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract Technological advances allow the production of increasingly complex electronic systems. Nevertheless, technology and voltage scaling increased dramatically the susceptibility of new devices not only to Single Bit Upsets (SBU), but also to Multiple Bit Upsets (MBU). In safety critical applications, it is mandatory to provide fault-tolerant systems, providing high reliability while meeting applications requirements. The problem of reliability is particularly expressed within the memory which represents more than 80% of systems on chips. To tackle this problem we propose a new memory reliability techniques referred to as DPSR: Double Parity Single Redundancy. DPSR is designed to enhance computing systems resilience to SBU and MBU. Based on a thorough fault injection experiments, DPSR shows promising results; It detects and corrects more than 99.6% of encountered MBU and has an average time overhead of less than 3%. Keywords Reliability · MBU · Fault injection · Memory
1 Introduction Thanks to manufacturing process and integration improvements, modern mobile and embedded systems are now able to execute complex applications with advanced functionalities, such driver assistant systems in autonomous automotive, drones etc. Consequently, System-on-chip (SoC) architectures are becoming increasignly complex and the underlying hardware has a particular impact on the energy consumption, performance and reliability. In fact, soft errors phenomenon Alexandre Chabot
[email protected] Ihsen Alouani [email protected] R´eda Nouacer [email protected] Smail Niar [email protected] 1
LAMIH, UMR CNRS, Universit´e Polytechnique Hauts-de-France, Famars, France
2
CEA-LIST, Palaiseau, France
3
IEMN, UMR CNRS, Universit´e Polytechnique Hauts-de-France, Famars, France
represents a serious challenge to new computing systems. Soft errors result from a voltage transient event induced by alpha particles from packaging material or neutron particles from cosmic rays [1]. The event is created through the collection of charge at a p-n junction after a track of electron–hole pairs is generated. A sufficient amount of accumulated charge in the struck node may invert the state of a logic device, such as a latch, static random access memory (SRAM) cell, or logic gate, thereby introducing an error into the hit circuit. In past technologies, this issue was considered in a limited range of applications in which the circuits are operating under aggressive environmental conditions like aerospace applications. Nevertheless, shrinking the transistor size and reducing the supply voltage in new technologies result in a remarkable decrease of the capacitance per transistor leading to a higher vulnerability within circuits nodes [2]. Hence, so
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