Download Area and Power Efficient 2 Bit Multiplier by Using Enhanced Half Adder

Queue processing for download document In this paper, a novel design of half adder (HA) is proposed using low power and area-efficient XOR and AND gates. Multipliers are essential component mostly used arithmetic unit. Using novel HA, novel design of multiplier and its area utilization is disc

You can start your download in 30 seconds

Recommend Documents
128-Bit Multiplier with Low-Area High-Speed Adder Based on Vedic Mathematics

149 31 26MB

Power and Delay Efficient ALU Using Vedic Multiplier

178 39 63MB

Low-Power Area-Efficient Fault Tolerant Adder in Current Mode Multi Valued Logic Using Berger Codes

156 58 2MB

PERAM: Ultra Power Efficient Array Multiplier Using Reversible Logic for High-Performance MAC

143 4 43MB

Power and Area-Efficient Architectural Design Methodology for Nanomagnetic Computation

161 24 16MB

Design of an Area Efficient and Low Power MAC Unit

180 27 759KB

Area and power efficient DCT architecture for image compression

195 92 1MB

High-Efficient, Ultra-Low-Power and High-Speed 4:2 Compressor with a New Full Adder Cell for Bioelectronics Applications

167 67 3MB

Low Power Radix-8 Modulo \(2^n+1\) Multiplier Using Modified Weighted Method

164 96 14MB

Truncated Multiplier with Delay-Minimized Exact Radix-8 Booth Recoder Using Carry Resist Adder

137 42 2MB

Signal aware energy efficient approach for low power full adder design with adiabatic logic

158 51 1MB

Low power 9-bit 500 kS/s 2-stage cyclic ADC using OTA variable bias current

144 52 1MB